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| Number | Title | Issue Date |
| 8185720 | Processor block ASIC core for embedding in an integrated circuit A hardwired core is embedded in an integrated circuit having programmable circuitry. The hardwired core has a microprocessor; a crossbar interconnect coupled to processor local buses of the microprocessor; and a memory controller interface coupled to the crossbar in... | 05/22/2012 |
| 8181140 | T-coil network design for improved bandwidth and electrostatic discharge immunity A method of generating a circuit design comprising a T-coil network includes determining inductance for inductors and a parasitic bridge capacitance of the T-coil network. The parasitic bridge capacitance is compared with a load capacitance metric that depends upon ... | 05/15/2012 |
| 8166431 | Reducing startup time of an embedded system that includes an integrated circuit A method of reducing startup time of an embedded system can include: instantiating a circuit, specified by a first circuit design, within an integrated circuit (IC), booting a first build of an operating system executed by a processor to a steady state, and responsi... | 04/24/2012 |
| 8161249 | Method and apparatus for multi-port arbitration using multiple time slots An apparatus includes a programmable device that has an interface and command ports that can each receive commands, each command requesting an information transfer through the interface. A technique relating to the device involves: selecting during field programming... | 04/17/2012 |
| 8161212 | Data operations across parallel non-volatile input/output devices An embodiment of a system for implementing parallel usage of a plurality of non-volatile input/output (I/O) devices can include an interface configured to receive, from a source, a source request and a first memory coupled to the interface. The first memory can be c... | 04/17/2012 |
| 8156456 | Unified design methodology for multi-die integrated circuits A method of designing an integrated circuit (IC) having multiple dies can include identifying a unified design library having a first process node specific (PNS) library for a first IC process technology and a second PNS library for a second IC process technology. T... | 04/10/2012 |
| 8154989 | Recovering a shared channel within a network from a deadlock state A method of processing data within a controller for a network can include identifying frames within a data stream within the network (1110) and detecting a deadlock state according to a number of consecutive frames comprising at least one set control bit (... | 04/10/2012 |
| 8150638 | Predicting parasitic capacitance in schematic circuit simulations using sub-circuit modeling A computer-implemented method of determining parasitic capacitance for transistors within an integrated circuit can include determining a first set of coefficients for a first expression that calculates parasitic capacitance for a transistor structure according to a... | 04/03/2012 |
| 8146041 | Latch based optimization during implementation of circuit designs for programmable logic devices A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed u... | 03/27/2012 |
| 8146027 | Creating interfaces for importation of modules into a circuit design A computer-implemented method of incorporating a module within a circuit design can include, responsive to identifying the module to be imported into the circuit design, automatically identifying each port of the module, displaying a list of the ports of the module,... | 03/27/2012 |
| 8144825 | Predicting clock period in a semiconductor device A computer-implemented method of predicting a clock period within an integrated circuit can include determining configuration information for the integrated circuit (1430, 1435, 1445) and determining at least one measure of directional shift for an edge of a ... | 03/27/2012 |
| 8143987 | Stacked dual inductor structure The dual inductor structure can include a first inductor including a first plurality of coils. Each coil of the first plurality of coils can be disposed within a different one of a plurality of conductive layers. The coils of the first plurality of coils can be vert... | 03/27/2012 |
| 8143695 | Contact fuse one time programmable memory A fuse structure for a semiconductor integrated circuit (IC) can include a first node comprising a region of a metal layer of an IC manufacturing process and a second node comprising a region of a conductive layer residing on a layer of the IC manufacturing process ... | 03/27/2012 |
| 8141010 | Method and arrangement providing for implementation granularity using implementation sets A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node ... | 03/20/2012 |
| 8136073 | Circuit design fitting Circuit design fitting for an integrated circuit is described. A mapped design for the circuit design is obtained. A first placement of the mapped design in association with an integrated circuit is performed. Circuit blocks are marked associated with the integrated... | 03/13/2012 |
| 8134878 | Signal calibration for memory interface A method of calibrating memory controller signals within an integrated circuit (IC) can include determining an internal delay of a clock network of the IC and generating a calibrated clock signal by applying a first delay to an uncalibrated clock signal, wherein the... | 03/13/2012 |
| 8134875 | Data storage system with removable memory module having parallel channels of DRAM memory and flash memory A data storage system includes a first circuit board, a plurality of sockets coupled to the first circuit board, an connector coupled to each of the sockets for coupling each of the sockets to external circuitry, and a plurality of memory modules, each memory module... | 03/13/2012 |
| 8122420 | Congestion elimination using adaptive cost schedule to route signals within an integrated circuit A computer-implemented method of routing a circuit design for a target integrated circuit (IC) can include determining a characterization of routing congestion of the circuit design within the target IC and determining a first order cost component of using routing r... | 02/21/2012 |
| 8122414 | Placeholder-based design flow for creating circuit designs for integrated circuits Within a system comprising a processor and a memory, a method of creating a circuit design for implementation within an integrated circuit can include inserting a placeholder block into the circuit design, wherein the circuit design includes a circuit block comprisi... | 02/21/2012 |
| 8117577 | Determining timing paths within a circuit block of a programmable integrated circuit A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a m... | 02/14/2012 |
| 8116162 | Dynamic signal calibration for a high speed memory controller Within an integrated circuit comprising a memory controller, a method can include, responsive to determining that the memory controller is performing a refresh operation, calculating a new tap setting according to a new maximum value and an old tap setting of the de... | 02/14/2012 |
| 8116119 | Desensitizing static random access memory (SRAM) to process variations A static random access memory (SRAM) can include a plurality of columns forming a memory array, wherein each column comprises a plurality of memory cells coupled to bitlines and wordlines, and a write replica circuit generating a signal when data has been written to... | 02/14/2012 |
| 8104012 | System and methods for reducing clock power in integrated circuits Dynamic power savings and efficient use of resources are achieved in a programmable logic device (PLD) such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD) by receiving a design netlist specifying a circuit including clock signa... | 01/24/2012 |
| 8104011 | Method of routing a design to increase the quality of the design A method of circuit design for an integrated circuit (IC) can include identifying a plurality of routing resources, wherein each of the plurality of routing resources is associated with a reliability measure, and selecting routing resources for use in routing a circ... | 01/24/2012 |
| 8103992 | Rapid rerouting based runtime reconfigurable signal probing A computer-implemented method of probing a design under test (DUT) instantiated within a programmable logic device (PLD) can include disabling a clock signal provided to the DUT (340) and generating a partial bitstream specifying a new probe for the DUT (3... | 01/24/2012 |
| 8102019 | Electrically programmable diffusion fuse A fuse structure for a semiconductor integrated circuit (IC) includes an anode comprising conductive material overlaying a diffusion material disposed within a substrate layer of the IC, wherein the diffusion material is electrically isolated from the substrate laye... | 01/24/2012 |
| 8099564 | Programmable memory controller A memory controller implemented within a programmable integrated circuit can include a user interface having a command register and a plurality of data First-In-First-Out (FIFO) memories, wherein the command register can receive an address of a data FIFO memory of t... | 01/17/2012 |
| 8091060 | Clock domain partitioning of programmable integrated circuits A computer-implemented method of partitioning a circuit design into clock domains for implementation within a programmable integrated circuit (IC) can include storing a plurality of constraints that depend upon a plurality of variables, wherein the plurality of cons... | 01/03/2012 |
| 8082532 | Placing complex function blocks on a programmable integrated circuit A computer-implemented method of implementing a circuit design within an integrated circuit (IC) can include, within an undirected graph representing the circuit design comprising nodes and edges, wherein each node represents a complex function block (CFB) or a pre-... | 12/20/2011 |
| 8082530 | Power estimation in high-level modeling systems A computer-implemented method of estimating power usage for high-level blocks of a high-level modeling system (HLMS) circuit design can include generating a low-level circuit design from the HLMS circuit design. The method can include simulating the low-level circui... | 12/20/2011 |
| 8079013 | Hardware description interface for a high-level modeling system A computer-implemented method of specifying a circuit design within a high-level modeling system (HLMS) can include, responsive to a scripted user input, instantiating a first and a second block objects within a hardware description interface (HDI) that is communica... | 12/13/2011 |
| 8077526 | Low power SSTL memory controller An integrated circuit device having configurable resources is configured as a memory controller that includes a plurality of bi-directional pins, an input buffer circuit that is operable to receive SSTL-compliant input and an output buffer that is operable to genera... | 12/13/2011 |
| 8074077 | Securing circuit designs within circuit design tools A method of securing a circuit design can include generating a string including a plurality of elements. The plurality of elements can include elements of design information selected from within the circuit design and at least one security element indicating whether... | 12/06/2011 |
| 8065644 | Reducing susceptibility of circuit designs to single event upsets A computer-implemented method of reducing susceptibility of a circuit design to single event upsets can include determining a susceptibility level of the circuit design to single event upsets, comparing the susceptibility level with a target susceptibility, and sele... | 11/22/2011 |
| 8065642 | Isolation verification for implementing modular redundancy within programmable integrated circuits A computer-implemented method of verifying isolation of a plurality of instances of a redundant module of a circuit design that is implemented within a single, programmable integrated circuit can include counting component failures needed to establish a connection b... | 11/22/2011 |
| 8065570 | Testing an integrated circuit having configurable input/output terminals Testing an integrated circuit (IC) having numerous terminals coupled to numerous digitally controlled impedance (DCI) modules, where the numerous DCI modules control configurable impedances of the numerous terminals. The IC further includes a control circuit having ... | 11/22/2011 |
| 8065445 | On-demand switching between hardware and software implementations of a peripheral device A method of accessing a peripheral device can include determining whether the peripheral device is busy. The method can include selectively providing to a processor, according to whether the peripheral device is busy, either a driver or a program. The driver, when e... | 11/22/2011 |
| 8063660 | Method and apparatus for configurable address translation A technique is applicable to a device having programmable circuitry that includes a first interface having a plurality of first address terminals, a second interface having a plurality of second address terminals, and a configurable interconnect structure coupled be... | 11/22/2011 |
| 8058905 | Clock distribution to facilitate gated clocks Circuits and methods for facilitating distribution of gated clocks in a programmable integrated circuit such as a field programmable gate array (FPGA) are described. Dynamic power savings are achieved in a FPGA by providing gated clock driver circuitry at various pl... | 11/15/2011 |
| 8058897 | Configuration of a multi-die integrated circuit A method of configuring an integrated circuit (IC) can include receiving configuration data within a master die of the IC. The IC can include the master die and a slave die. A master segment and a slave segment of the configuration data can be determined. The slave ... | 11/15/2011 |
