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| Number | Title | Issue Date |
| 6031427 | System for sweeping a phase lock loop into lock with automatic initiation and shutdown A phase locked loop ("PLL") 28 containing apparatus for automatically causing the PLL to achieve phase lock when first energized or after having lost phase lock. In addition to a phase detector 4, loop filter 13, voltage controlled oscillator ("VCO") 14 a... | 02/29/2000 |
| 6025589 | Apparatus and method for normalizing multiple color signals Color optical sensor array (11) having a color optical sensor (13) with each color optical sensor (13) having a color photodetector (56) and an active integrator circuit. The active integrator circuit having an operational amplifier (50) and an integratin... | 02/15/2000 |
| 6008746 | Method and apparatus for decoding noisy, intermittent data, such as manchester encoded data or the like According to a broad aspect of the invention, an apparatus (34) for decoding a Manchester encoded data stream is provided. The apparatus includes a transition detector (45) for receiving the Manchester encoded data stream to produce a transition indicatin... | 12/28/1999 |
| 5948080 | System for assigning a received data packet to a data communications channel by comparing portion of data packet to predetermined match set to check correspondence for directing channel select signal DMA channel receive packet comparator logic (74) of PCI-interface ASIC (20) assigns a data packet (106) through a data communications channel and includes DMA channel comparator logic (110) for receiving at least a portion of an incoming data packet (108)... | 09/07/1999 |
| 5949132 | Dambarless leadframe for molded component encapsulation A method and apparatus for encapsulating an integrated circuit die and leadframe assembly using dambarless leadframes. Dambarless leadframe 191 is formed having leads 193 that are widened in the region near the package edge such that the interlead spacing... | 09/07/1999 |
| 5943551 | Apparatus and method for detecting defects on silicon dies on a silicon wafer An apparatus and method for detecting defects on silicon dies on a silicon wafer (16) comprising an image acquisition system (10) and a computer (32) that determines a statistical die model by analyzing a random selection of dies (42) within a die matrix ... | 08/24/1999 |
| 5895967 | Ball grid array package having a deformable metal layer and method A ball grid array package (62) having a deformable metal layer (20) is provided that includes a heat spreader (60), a stiffener (40) having a cavity and mounted to the heat spreader (60), a substrate (22), and a die (50). The substrate (22) includes a die... | 04/20/1999 |
| 5891377 | Dambarless leadframe for molded component encapsulation A method and apparatus for encapsulating an integrated circuit die and leadframe assembly using dambarless leadframes. Dambarless leadframe 191 is formed having leads 193 that are widened in the region near the package edge such that the interlead spacing... | 04/06/1999 |
| 5888443 | Method for manufacturing prepackaged molding compound for component encapsulation A method and apparatus for providing a prepackaged mold compound for use in encapsulating integrated circuit die and leadframe assemblies. A piece of mold compound 71 is placed in a receptacle 91 in a bottom mold chase 83. The receptacle 91 is coupled to ... | 03/30/1999 |
| 5885506 | Pre-packaged molding for component encapsulation A method and apparatus for encapsulating an integrated circuit die and leadframe assembly. A prepackaged mold compound insert 71 is placed in a rectangular receptacle 91 in a bottom mold chase 81. The receptacle is coupled to a plurality of die cavities 8... | 03/23/1999 |
| 5859456 | Multiple transistor integrated circuit with thick copper interconnect An interconnection structure and method for a multiple transistor integrated circuit power device is disclosed. A power integrated circuit is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain o... | 01/12/1999 |
| 5849132 | Ball contact for flip-chip devices A contact for a semiconductor device or passive substrate is made up of an array of conductive balls, the individual balls of the contact being a compressible material coated with a metal conductive material. The balls in the array are compressed while be... | 12/15/1998 |
| 5798564 | Multiple chip module apparatus having dual sided substrate The invention is to a double side semiconductor module (10) and an array (40) made up of a plurality of stacked modules (10). Each module (10) includes a plurality of substrates (11-15). A first substrate (13) has first and second sides, with one semicond... | 08/25/1998 |
| 5793068 | Compact gate array The gate array (10) has a first doped region (14) in a semiconductor substrate (12) and a plurality of contacts (20-20"', 21-21") arranged in rows and columns to the first doped region (14) organized with contacts of each row offset in a column (25) that ... | 08/11/1998 |
| 5739570 | Integrated circuit An integrated circuit (42) is formed in a semiconductor layer (50) having a defined area. Functional circuitry (12) is formed in semiconductor layer (50) to occupy only a portion of the defined area of semiconductor layer (50), and thus defining an unoccu... | 04/14/1998 |
| 5728594 | Method of making a multiple transistor integrated circuit with thick copper interconnect An interconnection structure and method for a multiple transistor integrated circuit power device is disclosed. A power integrated circuit is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain o... | 03/17/1998 |
| 5710456 | Silver spot/palladium plate lead frame finish A lead frame is plated with palladium and then selected portions of the lead frame leads are spot plated with silver to improve solderability.... | 01/20/1998 |
| 5698038 | Method for wafer carrier cleaning A method for cleaning a wafer carrier. A tank having sides and a bottom is provided. A weir is provided within the tank and having sides lower than the sides of the tank. Nozzles for outputting pressurized solution are provided within the weir. Laminar fl... | 12/16/1997 |
| 5675241 | Voltage regulator with low drop out voltage A circuit and method for providing a low drop out voltage regulator. A source follower circuit is provided having a transistor (MD1) with an output terminal for driving a load at its source terminal and a voltage supply coupled to the drain terminal. At l... | 10/07/1997 |
| 5673219 | Apparatus and method for reducing leakage current in a dynamic random access memory In a dynamic random access memory unit, the leakage current from a non-selected charged storage cell capacitor (320-324; 325-329) through the pass transistor (310-314; 315-319) to a zero voltage bitline (31, 32) is reduced by first isolating the bitline p... | 09/30/1997 |
| 5672962 | Frequency compensated current output circuit with increased gain A frequency compensated current output circuit with increased gain. The current output circuit is an improved current mirror where the gate of an output transistor (MP06) is coupled to an impedance (Ra) located in the conductive path of the mirror transis... | 09/30/1997 |
| 5641701 | Method for fabricating a semiconductor device with laser programable fuses A method for fabricating a semiconductor device includes the steps of: forming fuses (40) and conductive pads (46) above a semiconductor substrate (43); depositing a layer of cap oxide (44) over the fuses and the conductive pads; sintering the cap oxide; ... | 06/24/1997 |
| 5585657 | Windowed and segmented linear geometry source cell for power DMOS processes A source cell having reduced area and reduced polysilicon window width requirements for use as the source region in a DMOS transistor is disclosed, comprising: a source region of semiconductor material disposed on a semiconductor substrate; a plurality of... | 12/17/1996 |
| 5545846 | Laser bond header The invention is to a header for a power semiconductor device and a method for making the header. A ground pin is mounted or formed on the header mounting base and a header ground lead is placed over the ground pin and fused to the pin by a laser beam.... | 08/13/1996 |
| 5519341 | Cross coupled quad comparator for current sensing independent of temperature A circuit and method for sensing and limiting current. A resistor (R1) is used to generate a voltage (V1) proportional to the current flowing in an output transistor (M1). A comparator is formed in a cross coupled quad configuration from bipolar transisto... | 05/21/1996 |
| 5512130 | Method and apparatus of etching a clean trench in a semiconductor material An etching apparatus (10) includes a process chamber (12) partially surrounded by an upper electrode (14) and a lower electrode (16). A semiconductor material (18) lies within the process chamber (12) and in contact with the lower electrode (16). The lowe... | 04/30/1996 |
| 5508519 | Mainshaft shield A system for removal of contaminating particles from a target chamber (1) which includes a target chamber having an aperture in the floor thereof for entry of a reciprocating shaft (7) for positioning a wafer (11) within the target chamber, a seal (21) di... | 04/16/1996 |
| 5500625 | Controlled current output stage amplifier circuit and method An amplifier circuit (10) is provided. The amplifier (10) includes an amplifier stage (14) coupled to an output stage (18). Output stage (18) comprises a sourcing circuit (20) and a sinking circuit (22). The current in sinking circuit (22) is approximatel... | 03/19/1996 |
| 5495487 | Testing buffer/register A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs ... | 02/27/1996 |
| 5489862 | Output driver with slew and skew rate control An output driver circuit for use with low voltage level, high speed data transmission busses which require slew and skew control of the output voltage transitions. An open collector output transistor has a controlled slew rate for both the high to low and... | 02/06/1996 |
| 5483518 | Addressable shadow port and protocol for serial bus networks A protocol and associated circuitry operable for efficiently extending serial bus capability in system environments is described. The protocol is designed to coexist and be fully compatible with existing serial bus approaches, and in particular an example... | 01/09/1996 |
| 5468984 | ESD protection structure using LDMOS diodes with thick copper interconnect An interconnection structure and method for a multiple zener diode ESD protectoin circuit for power semiconductor devices. A plurality of lateral Zener diodes is formed. Each device is formed of a plurality of cathode and anode diffusion regions to be cou... | 11/21/1995 |
| 5463359 | Impedance matching network for low output impedance devices An impedance matching circuit which includes an RC network placed at the end of the transmission line and which will absorb reflections. The values of the resistor and capacitor are selected such that the output voltage at the end of the transmission line... | 10/31/1995 |
| 5457624 | Efficient switched mode power converter circuit and method A method and apparatus are disclosed for sustaining efficiency of switched mode power converters over wide load ranges. The method and apparatus can be used with any switched mode power converter having at least one synchronous rectifier (Q2) c... | 10/10/1995 |
| 5457411 | Trinary logic input gate A trinary input logic gate (25). A first output transistor (36) is coupled to a first voltage output (V01) and pulls the voltage output to a high voltage in response to a voltage input (VIN) below a defined low threshold. A second ou... | 10/10/1995 |
