Cooper; Kent J. - US Patent Attorneys and Agents

Attorney: Cooper; Kent J.

Number of patents: 31
Last date: January 13, 2004

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Number	Title	Issue Date
6677226	Method for forming an integrated circuit having a bonding pad and a fuse In one embodiment, a first dielectric layer (32) that overlies a fuse (16) and a bonding pad (30) is etched with a first etch process. This first etch process exposes a portion (40) of a second dielectric layer (20) that underlies the first dielectric lay...	01/13/2004
6147510	Integrated circuit for handling buffer contention and method thereof In one embodiment, an integrated circuit (10, 110) has a contention detection circuit (12, 112) coupled to a tri-stateable output buffer (18, 118). The contention detection circuit (12, 112) provides a contention tri-state control signal (34, 134) to the ...	11/14/2000
6100196	Method of making a copper interconnect with top barrier layer A method for making copper interconnections in an integrated circuit is described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of coppe...	08/08/2000
5901103	Integrated circuit having standby control for memory and method thereof An integrated circuit (10) contains a central processing unit (CPU) (12) and a plurality of memory blocks (26-34) configured into one or more banks of memory. A plurality of power control switches (38-42) are used to dynamically select which of a pluralit...	05/04/1999
5885870	Method for forming a semiconductor device having a nitrided oxide dielectric layer In one embodiment a non-volatile memory device having improved reliability is formed by oxidizing a first portion of a semiconductor substrate (12) to form a first silicon dioxide layer (14). The first silicon dioxide layer (14) is then annealed and secon...	03/23/1999
5872385	Conductive interconnect structure and method of formation In one embodiment, delamination of a patterned silicon nitride anti-reflective layer (26) from an underlying patterned tungsten silicide layer (32), is prevented by forming a thin silicon layer (30) between the patterned tungsten silicide layer (32) and t...	02/16/1999
5786263	Method for forming a trench isolation structure in an integrated circuit The reliability of integrated circuits fabricated with trench isolation is improved by forming a trench isolation structure with a void-free trench plug (36). In one embodiment, a polysilicon layer (28) is formed within a trench (22) and then subsequently...	07/28/1998
5639687	Method for forming an integrated circuit pattern on a semiconductor substrate using silicon-rich silicon nitride Reflective notching of a photoresist pattern (20), generated over reflective materials on a semiconductor substrate (12), is minimized by using an anti-reflective layer (20) of silicon-rich silicon nitride. The layer of silicon-rich silicon nitride is for...	06/17/1997
5624854	Method of formation of bipolar transistor having reduced parasitic capacitance Vertically stacked regions of n-type and p-type conductivity are formed around bipolar and field effect transistors to reduce parasitic capacitance between the semiconductor device and surrounding well regions. Under reverse bias a portion of the vertical...	04/29/1997
5604159	Method of making a contact structure The horizontal surface area required to contact semiconductor devices, in integrated circuits fabricated with trench isolation, is minimized without degrading contact resistance by utilizing the vertical surface area of the trench sidewall. A trench isola...	02/18/1997
5556506	Method for forming a conductive layer of material on an integrated circuit substrate In one embodiment a plasma ignitor (10) having a first dielectric housing (18), that encases a first portion of a first conductive lead (14) and a first portion of a second conductive lead (16), and end cap (30), that locks its filament (31) into position...	09/17/1996
5543635	Thin film transistor and method of formation An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing...	08/06/1996
5538922	Method for forming contact to a semiconductor device A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over...	07/23/1996
5539249	Method and structure for forming an integrated circuit pattern on a semiconductor substrate Reflective notching of a photoresist pattern (20), generated over reflective materials on a semiconductor substrate (12), is minimized by using an anti-reflective layer (20) of silicon-rich silicon nitride. The layer of silicon-rich silicon nitride is for...	07/23/1996
5510278	Method for forming a thin film transistor An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing...	04/23/1996
5503958	Method for forming a circuit pattern In one embodiment of the invention x-rays pass through an aluminum filter (18) to form filtered x-rays. At least a portion of the filtered x-rays then pass through a portion of a x-ray mask (22) to expose a portion of a photoresist layer overlying a semic...	04/02/1996
5504363	Semiconductor device Vertically stacked regions of n-type and p-type conductivity are formed around bipolar and field effect transistors to reduce parasitic capacitance between the semiconductor device and surrounding well regions. Under reverse bias a portion of the vertical...	04/02/1996
5494838	Process of making EEPROM memory device having a sidewall spacer floating gate electrode An EEPROM memory array includes a plurality of memory cells having a floating gate electrode (22) formed as a sidewall spacer adjacent to a control gate electrode (20). Source and drain regions (12, 14) reside in a semiconductor substrate (10) and define ...	02/27/1996
5445107	Semiconductor device and method of formation A silicon-on insulator film (38) is formed by solid phase epitaxial re-growth. A layer of amorphous silicon (36) is formed such that it is only in direct contact with an underlying portion of a silicon substrate (12). The layer of amorphous silicon (36) i...	08/29/1995
5441914	Method of forming conductive interconnect structure In one embodiment, delamination of a patterned silicon nitride anti-reflective layer (26) from an underlying patterned tungsten silicide layer (32), is prevented by forming a thin silicon layer (30) between the patterned tungsten silicide layer (32) and t...	08/15/1995
5436488	Trench isolator structure in an integrated circuit The reliability of integrated circuits fabricated with trench isolation is improved by increasing the thickness of the gate dielectric overlying the trench corner. After the trench isolation region (40, 56) has been formed a thin layer of silicon dioxide ...	07/25/1995
5433650	Method for polishing a substrate A semiconductor substrate (48) and a block of optical quartz (50) are simultaneously polished. An interferometer (22), in conjunction with a data processing system (16), are then used to monitor the thickness and the polishing rate of the optical quartz b...	07/18/1995
5422300	Method for forming electrical isolation in an integrated circuit Defect-free field oxide isolation is achieved using a laminated layer (14) of thermal silicon dioxide and chemically vapor deposited silicon dioxide underneath a silicon nitride field oxidation mask (18). The laminated layer (14) of silicon dioxide is for...	06/06/1995
5420072	Method for forming a conductive interconnect in an integrated circuit A conformal titanium nitride film having a preferred crystal orientation is formed by chemically vapor depositing the film in two separate steps. In the first deposition step a titanium nitride layer (22) having poor step coverage and a preferred	05/30/1995
5405806	Method for forming a metal silicide interconnect in an integrated circuit A metal silicide interconnect (48, 92, 124) is formed in an integrated circuit using a sacrificial layer (30, 78, 108). In one embodiment a sacrificial layer of titanium nitride (30) is formed overlying a semiconductor substrate (12) and a polysilicon con...	04/11/1995
5406111	Protection device for an intergrated circuit and method of formation An input/output protection device for an integrated circuit is formed using a trench (22). A first electrode region (46) is formed adjacent a first portion of the trench sidewall (24), and a second electrode region (48) is formed adjacent a second portion...	04/11/1995
5387540	Method of forming trench isolation structure in an integrated circuit The reliability of integrated circuits fabricated with trench isolation is improved by increasing the thickness of the gate dielectric overlying the trench corner. After the trench isolation region (40, 56) has been formed a thin layer of silicon dioxide ...	02/07/1995
5378659	Method and structure for forming an integrated circuit pattern on a semiconductor substrate Reflective notching of a photoresist pattern (20), generated over reflective materials on a semiconductor substrate (12), is minimized by using an anti-reflective layer (20) of silicon-rich silicon nitride. The layer of silicon-rich silicon nitride is for...	01/03/1995
5374573	Method of forming a self-aligned thin film transistor A thin film transistor with self-aligned source and drain regions is fabricated, in one embodiment, by forming an opening (124) in a dielectric layer (118) which overlies a substrate (116). A semiconductive sidewall spacer (130) is formed around the perim...	12/20/1994
5371035	Method for forming electrical isolation in an integrated circuit device A layer of silicon-germanium (57) allows electrical isolation structures, having reduced field oxide encroachment, to be formed without adversely effecting the adjacent active regions (64). A high etch selectivity between silicon-germanium and the silicon...	12/06/1994
5351419	Method for vapor drying A multi-directional flow of isopropyl alcohol vapor is used to uniformly dry a semiconductor substrate. In one embodiment of the invention, isopropyl alcohol vapor (19), which is generated by an external vapor source (30), is injected into the vapor dryin...	10/04/1994

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Attorney: Cooper; Kent J.