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A vest or belt is integrally formed with tubular, pet receiving passageways which extend around the wearer's body and terminate in pocket-like chambers for feeding and retrieval.
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| Number | Title | Issue Date |
| 6581029 | Method and system for optimizing execution of a collection of related module sequences by eliminating redundant modules A method and system for optimizing the execution of a collection of related modules by eliminating redundant modules from the collection. The collection of modules represent a set of related simulation experiments and are organized as generations of relat... | 06/17/2003 |
| 6492262 | Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies Method and structures for making a highly reliable metal interlock structure with continuous via and line structures. The absence of barrier layers between vias and lines or absence of interlevel dielectric layer is used to enhance chip performance.... | 12/10/2002 |
| 6373339 | Active bias network circuit for radio frequency amplifier A bias network for a radio frequency signal power amplifier. A current source is connected to a source of band gap voltage and produces a current proportional to the voltage. A reference voltage circuit receives the current and produces a voltage which is... | 04/16/2002 |
| 6339258 | Low resistivity tantalum An alpha-phase tantalum having a resistivity of about 15 micro-ohm-cm or less is provided and is especially useful as a barrier layer for copper and copper alloy interconnections.... | 01/15/2002 |
| 6337218 | Method to test devices on high performance ULSI wafers An apparatus for testing structures in semiconductor wafers. The apparatus includes at least one test probe. At least one tool measures and controls deceleration of the at least one test probe as it approaches a surface of a structure in the semiconductor... | 01/08/2002 |
| 6337151 | Graded composition diffusion barriers for chip wiring applications A barrier film for a semiconductor device structure. The barrier film includes a compound including nitrogen and at least one of titanium or tantalum, nitrogen in a concentration that varies within the barrier film, and oxygen in a concentration that vari... | 01/08/2002 |
| 6335262 | Method for fabricating different gate oxide thicknesses within the same chip A semiconductor structure having silicon dioxide layers of different thicknesses is fabricated by forming a sacrificial silicon dioxide layer on the surface of a substrate; implanting nitrogen ions through the sacrificial silicon dioxide layer into first ... | 01/01/2002 |
| 6333560 | Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies Method and structures for making a highly reliable metal interlock structure with continuous via and line structures. The absence of barrier layers between vias and lines or absence of interlevel dielectric layer is used to enhance chip performance.... | 12/25/2001 |
| 6297140 | Method to plate C4 to copper stud A method for plating a second metal directly to a first metal without utilizing a mask. A semiconductor substrate is provided including at least one metal feature and at least one insulating layer covering the metal feature and the substrate. At least one... | 10/02/2001 |
| 6291858 | Multistack 3-dimensional high density semiconductor device and method for fabrication A multistack 3-D semiconductor structure comprising a first level structure comprising a first semiconductor substrate and first active devices; and a second level structure comprising a SOI semiconductor structure bonded to the first level structure and ... | 09/18/2001 |
| 6268640 | Forming steep lateral doping distribution at source/drain junctions A semiconductor device is fabricated by implanting into a semiconductor substrate non-doping ions at a tilt angle of at least about 10° to laterally extend preamorphization of the substrate portion and then implanting into the substrate dopants for provi... | 07/31/2001 |
| 6261876 | Planar mixed SOI-bulk substrate for microelectronic applications A process for creating a substrate including bulk silicon regions and semiconductor-on-insulator regions. Regions of a surface of a bulk silicon substrate are recessed above regions where it is desired to create buried oxide regions in the substrate. Impl... | 07/17/2001 |
| 6258717 | Method to produce high quality metal fill in deep submicron vias and lines A process for plating metal in submicron structures. A seedlayer is deposited on surfaces of submicron structures. The seedlayer is annealed at a temperature of about 80° C. to about 130° C. Metal is plated on the seedlayer.... | 07/10/2001 |
