Conley, Rose & Tayon, P.C., Merkel; Lawrence J. - US Patent Attorneys and Agents

Attorney: Conley, Rose & Tayon, P.C., Merkel; Lawrence J.

Number of patents: 28
Last date: February 13, 2001

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Number	Title	Issue Date
6189068	Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle A superscalar microprocessor employing a data cache configured to perform store accesses in a single clock cycle is provided. The superscalar microprocessor speculatively stores data within a predicted way of the data cache after capturing the data curren...	02/13/2001
6157994	Microprocessor employing and method of using a control bit vector storage for instruction execution A control bit vector storage is provided. The present control bit vector storage (preferably included within a functional unit) stores control bits indicative of a particular instruction. The control bits are divided into multiple control vectors, each ve...	12/05/2000
6157993	Prefetching data using profile of cache misses from earlier code executions During execution of a code sequence, a profile is generated containing addresses of the data cache misses experienced during the execution. The profile is associated with the code sequence such that, during a future execution of the code sequence, the pro...	12/05/2000
6138213	Cache including a prefetch way for storing prefetch cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line A cache employs one or more prefetch ways for storing prefetch cache lines and one or more ways for storing accessed cache lines. Prefetch cache lines are stored into the prefetch way, while cache lines fetched in response to cache misses for requests ini...	10/24/2000
6134651	Reorder buffer employed in a microprocessor to store instruction results having a plurality of entries predetermined to correspond to a plurality of functional units A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated wh...	10/17/2000
6134650	Apparatus and method for predicting a first scanned instruction as microcode instruction prior to scanning predecode data A superscalar microprocessor predecodes instruction data to identify the boundaries of instructions and the type of instruction. When the cache line is scanned for dispatch, the first scanned instruction is predicted to be a microcode instruction and is d...	10/17/2000
6134649	Control transfer indication in predecode which identifies control transfer instruction and an alternate feature of an instruction A processor is configured to predecode instruction bytes prior to storing them in an instruction cache. The predecode information generated by the processor includes instruction boundary indications identifying which of the instruction bytes are boundarie...	10/17/2000
6122729	Prefetch buffer which stores a pointer indicating an initial predecode position A prefetch/predecode unit includes one or more prefetch buffers which are configured to store prefetched sets of instruction bytes and corresponding predecode data. Additionally, each prefetch buffer is configured to store a predecode byte pointer. The pr...	09/19/2000
6122727	Symmetrical instructions queue for high clock frequency scheduling An instruction queue is physically divided into two (or more) instruction queues. Each instruction queue is configured to store a dependency vector for each instruction operation stored in that instruction queue. The dependency vector is evaluated to dete...	09/19/2000
6122656	Processor configured to map logical register numbers to physical register numbers using virtual register numbers A processor employing a map unit including register renaming hardware is shown. The map unit may assign virtual register numbers to source registers by scanning instruction operations to detect intraline dependencies. Subsequently, physical register numbe...	09/19/2000
6119223	Map unit having rapid misprediction recovery A processor employing a map unit including register renaming hardware is shown. The map unit may assign virtual register numbers to source registers by scanning instruction operations to detect intraline dependencies. Subsequently, physical register numbe...	09/12/2000
6115792	Way prediction logic for cache array A set-associative cache memory configured to use multiple portions of a requested address in parallel to quickly access data from a data array based upon stored way predictions. The cache memory comprises a plurality of memory locations, a plurality of st...	09/05/2000
6112293	Processor configured to generate lookahead results from operand collapse unit and for inhibiting receipt/execution of the first instruction based on the lookahead result A processor includes a lookahead address/result calculation unit which is configured to receive operand information (either the operand or a tag identifying the instruction which will produce the operand value) corresponding to the source operands of one ...	08/29/2000
6105129	Converting register data from a first format type to a second format type if a second type instruction consumes data produced by a first type instruction A microprocessor includes one or more registers which are architecturally defined to be used for at least two data formats. In one embodiment, the registers are the floating point registers defined in the x86 architecture, and the data formats are the flo...	08/15/2000
6101577	Pipelined instruction cache and branch prediction mechanism therefor A microprocessor includes an instruction cache having a cache access time greater than the clock cycle time employed by the microprocessor. The instruction cache is banked, and access to alternate banks is pipelined. The microprocessor also includes a bra...	08/08/2000
6097403	Memory including logic for operating upon graphics primitives A main memory comprises one or more memory devices which include logic for performing a predetermined graphics operation upon graphics primitives stored therein. The microprocessor(s) within the computer system may direct the memory to perform the predete...	08/01/2000
6094716	Register renaming in which moves are accomplished by swapping rename tags An apparatus for accelerating move operations includes a lookahead unit which detects move instructions prior to the execution of the move instructions (e.g. upon selection of the move operations for dispatch within a processor). Upon detecting a move ins...	07/25/2000
6088789	Prefetch instruction specifying destination functional unit and read/write access mode A microprocessor is configured to execute a prefetch instruction specifying a cache line to be transferred into the microprocessor, as well as an access mode for the cache line. The microprocessor includes caches optimized for the access modes. In one emb...	07/11/2000
6088781	Stride instruction for fetching data separated by a stride amount A microprocessor is configured to execute a stride instruction. In response to the stride instruction, the microprocessor performs a series of load memory operations. The address corresponding to a particular load memory operation is the sum of a stride o...	07/11/2000
6081656	Method for deriving a double frequency microprocessor from an existing microprocessor A first microprocessor having a PH1/PH2 pipeline structure is designed. The first microprocessor undergoes a design cycle including microarchitecture, design (e.g. logic design, circuit design, and layout work), verification, qualification, and volume man...	06/27/2000
6079005	Microprocessor including virtual address branch prediction and current page register to provide page portion of virtual and physical fetch address A microprocessor employs a branch prediction unit including a branch prediction storage which stores the index portion of branch target addresses and an instruction cache which is virtually indexed and physically tagged. The branch target index (if predic...	06/20/2000
6079003	Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache A microprocessor employs a branch prediction unit including a branch prediction storage which stores the index portion of branch target addresses and an instruction cache which is virtually indexed and physically tagged. The branch target index (if predic...	06/20/2000
6076151	Dynamic memory allocation suitable for stride-based prefetching A dynamic memory allocation routine maintains an allocation size cache which records the address of a most recently allocated memory block for each different size of memory block that has been allocated. Upon receiving a dynamic memory allocation request,...	06/13/2000
6076146	Cache holding register for delayed update of a cache line into an instruction cache An instruction cache employing a cache holding register is provided. When a cache line of instruction bytes is fetched from main memory, the instruction bytes are temporarily stored into the cache holding register as they are received from main memory. Th...	06/13/2000
6065103	Speculative store buffer A speculative store buffer is speculatively updated in response to speculative store memory operations buffered by a load/store unit in a microprocessor. Instead of performing dependency checking for load memory operations among the store memory operation...	05/16/2000
6058461	Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation A computer system includes one or more microprocessors. The microprocessors assign a priority level to each memory operation as the memory operations are initiated. In one embodiment, the priority levels employed by the microprocessors include a fetch pri...	05/02/2000
6055650	Processor configured to detect program phase changes and to adapt thereto A phase change monitor monitors one or more processor resources to detect a phase change in the program being executed. The phase change monitor signals a prefetch unit to indicate the detected phase change, and may also provide information regarding the ...	04/25/2000
6047363	Prefetching data using profile of cache misses from earlier code executions During execution of a code sequence, a profile is generated containing addresses of the data cache misses experienced during the execution. The profile is associated with the code sequence such that, during a future execution of the code sequence, the pro...	04/04/2000

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Attorney: Conley, Rose & Tayon, P.C., Merkel; Lawrence J.