Conley, Rose & Tayon, P.C., Kivlin; B. Noel - US Patent Attorneys and Agents

Attorney: Conley, Rose & Tayon, P.C., Kivlin; B. Noel

Number of patents: 20
Last date: October 31, 2000

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Number	Title	Issue Date
6141789	Technique for detecting memory part failures and single, double, and triple bit errors The bits of a data block are logically partitioned into an array that includes a number of columns equal to a number of memory devices and a number of rows equal to a number of bits of the data block stored in each memory device. Each memory device contri...	10/31/2000
6137716	Memory system using multiple storage mechanisms to enable storage and retrieval of more than two states in a memory cell A memory circuit which uses multiple storage mechanisms in each of its memory cells. In one embodiment, the memory circuit includes an array of cells in which each cell has multiple storage elements. At least one of the storage elements performs its funct...	10/24/2000
5905893	Microprocessor adapted for executing both a non-compressed fixed length instruction set and a compressed variable length instruction set A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. ...	05/18/1999
5799203	System for receiving peripheral device capability information and selectively disabling corresponding processing unit function when the device failing to support such function A system and method for providing information regarding system support capabilities to a processor. A computer system includes a processing unit, a main memory and a first plurality of peripherals coupled to a first bus. A bus bridge couples the first bus...	08/25/1998
5784011	Multiplier circuit for performing inverse quantization arithmetic An inverse quantizer includes a multiplier circuit using two adder/subtracter stages to perform a multiplication operation between the quantizer scale value and the weight value. The inverse quantizer may be employed within a video decoder circuit such an...	07/21/1998
5721945	Microprocessor configured to detect a DSP call instruction and to direct a DSP to execute a routine corresponding to the DSP call instruction A microprocessor including an instruction decode unit configured to detect a DSP call instruction is provided. The DSP call instruction is indicative of a call to a subroutine which performs a DSP function. Detected DSP call instructions are routed to a D...	02/24/1998
5687110	Array having an update circuit for updating a storage location with a value stored in another storage location A memory including first storage circuits for storing first values and second storages circuit for storing second values is provided. The first value may be retired branch prediction information, while the second value may be speculative branch prediction...	11/11/1997
5680578	Microprocessor using an instruction field to specify expanded functionality and a computer system employing same A microprocessor is provided which expands the functionality and/or performance of the implemented architecture in transparent and/or non-transparent ways. The microprocessor is configured to detect the presence of segment override prefixes in instruction...	10/21/1997
5671424	Immediate system management interrupt source with associated reason register A power management unit that includes a software writable enable register for receiving an SMI enable bit when the generation of an immediate SMI is desired. When the enable bit is set, an SMI flag register causes the assertion of an SMI signal. The power...	09/23/1997
5666505	Heuristic prefetch mechanism and method for computer system A heuristic prefetch mechanism that fetches code without solicitation by the execution unit. The prefetch mechanism is configured to normally prefetch sequential code and, if a particular line of requested code is out of sequence with respect to an immedi...	09/09/1997
5661751	System and technique for power management of a universal asynchronous receiver/transmitter by automatic clock gating A clock control unit is provided that controls the gating of a clock signal received by an internal baud generator of a universal asynchronous receiver/transmitter (UART) circuit during an active mode. The clock control unit monitors the UART circuit to d...	08/26/1997
5655142	High performance derived local bus and computer system employing the same An integrated processor is provided that includes a CPU core, a local bus coupled to the CPU core, and a variety of peripheral such as a memory controller, a direct memory access controller, and an interrupt controller coupled to the local bus. A bus inte...	08/05/1997
5640573	Power management message bus for integrated processor An integrated processor is provided that includes a CPU core coupled to a variety of on-chip peripheral devices such as a DMA controller, an interrupt controller, and a timer. The integrated processor further includes a power management message unit coupl...	06/17/1997
5638533	Method and apparatus for providing data to a parallel processing array A data register for providing data values to an n-element parallel processing array includes a memory buffer having first and second memory modules, where each module includes n columns of data values. An address decoder receives an address for accessing ...	06/10/1997
5630099	Non-volatile memory array controller capable of controlling memory banks having variable bit widths A non-volatile memory controller is provided which is connectable directly to the local bus of a computer system and which allows access to one or more 32-bit banks of ROM and to an 8-bit bank of non-volatile memory. The 8-bit bank of non-volatile memory ...	05/13/1997
5625807	System and method for enabling and disabling a clock run function to control a peripheral bus clock signal A system and method for controlling a peripheral bus clock signal through a master and/or slave device is provided that accommodates a power conservation (or "clock run") scheme in which a peripheral bus clock signal may be stopped, for example, by a powe...	04/29/1997
5623638	Memory control unit with programmable edge generator to minimize delay periods for critical DRAM timing parameters A system is disclosed for minimizing delays for critical timing parameters during DRAM transactions. The present invention comprises a modified memory control unit which includes a programmable DRAM edge generator for increasing the resolution times for a...	04/22/1997
5619464	High performance RAM array circuit employing self-time clock generator for enabling array accessess A RAM array circuit is provided which includes a memory array formed by several RAM cell columns. A particular cell within each column and row may be selected for access (either read or write) by an address decode circuit. The RAM array circuit employs a ...	04/08/1997
5600839	System and method for controlling assertion of a peripheral bus clock signal through a slave device A system and method for controlling a peripheral bus clock signal through a slave device are provided that accommodate a power conservation scheme in which a peripheral bus clock signal may be stopped, for example, by a power management unit or other cent...	02/04/1997
5596756	Sub-bus activity detection technique for power management within a computer system The computer system includes an integrated processor coupled to a power management unit and at least one peripheral device. The integrated processor includes a bus interface unit that provides an interface to a high performance peripheral interconnect bus...	01/21/1997

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Attorney: Conley, Rose & Tayon, P.C., Kivlin; B. Noel