Did You Know...
...that when IBM conducted a market study of Chester Carlson's invention in 1959, the company concluded that it would take only 5000 units of his new product to saturate the market? IBM therefore declined to be part of the new product introduction. Too bad for IBM. Carlson's invention was the xerography process, and his new product was the beginning of the Xerox Corporation. It is estimated that every day, worldwide, 3,000,000,000 copies are made!!
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| Number | Title | Issue Date |
| 6061521 | Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU may be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an... | 05/09/2000 |
| 6047372 | Apparatus for routing one operand to an arithmetic logic unit from a fixed register slot and another operand from any register slot A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an... | 04/04/2000 |
| 6017802 | Ultra-short transistor fabrication scheme for enhanced reliability A detached drain transistor including a semiconductor substrate, a gate dielectric formed on an upper surface of the substrate, a conductive gate formed on the gate dielectric, a first pair of spacer structures, a first source impurity distribution, a sec... | 01/25/2000 |
| 6013574 | Method of forming low resistance contact structures in vias arranged between two levels of interconnect lines A method of forming low resistance contact structures in vias arranged between interconnect levels is provided. The method involves interconnect lines having an anti-reflective layer formed thereupon. An interlevel dielectric layer is formed over the inte... | 01/11/2000 |
| 6009505 | System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an... | 12/28/1999 |
| 5985724 | Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spacer Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asym... | 11/16/1999 |
| 5970347 | High performance mosfet transistor fabrication technique A semiconductor fabrication process in which nitrogen is incorporated into the transistor gate without significantly increasing the resistivity of the source/drain region. The incorporation of nitrogen into the gate structure substantially reduces the mig... | 10/19/1999 |
| 5966766 | Apparatus and method for cleaning semiconductor wafer A method and apparatus for cleaning a semiconductor wafer. The apparatus preferably includes a brush holder that may include a base and a connection stud extending from the base. The base preferably includes a first plurality of openings and a receiving l... | 10/19/1999 |
| 5966116 | Method and logic system for the rotation of raster-scan display images A computer system is provided which employs a hardware rotation unit capable of rotating a raster-scan portrait image by 90 degrees in a clockwise or counter-clockwise direction in order to create a landscape image on a raster-scan display device. Rotatio... | 10/12/1999 |
| 5963809 | Asymmetrical MOSFET with gate pattern after source/drain formation A process for fabricating a transistor in which a first impurity distribution is introduced into a semiconductor substrate prior to the formation of a conductive gate structure on the semiconductor substrate. The substrate includes a channel region dispos... | 10/05/1999 |
| 5962914 | Reduced bird's beak field oxidation process using nitrogen implanted into active region A method of forming a self-aligned field oxide isolation structure without using silicon nitride. The method comprises forming a dielectric on an upper surface of a semiconductor substrate. The upper surface of the semiconductor substrate comprises an act... | 10/05/1999 |
| 5941938 | System and method for performing an accumulate operation on one or more operands within a partitioned register A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an... | 08/24/1999 |
| 5941968 | Computer system for concurrent data transferring between graphic controller and unified system memory and between CPU and expansion bus device A computer system is provided including a CPU, a graphics controller, system memory, data steering logic, a DMA controller and arbitration logic. The graphics controller and system memory are coupled to a high-speed data bus. Data accessed by the CPU, the... | 08/24/1999 |
| 5939874 | Voltage detection circuit having comparator pairs with mutually connected inputs A voltage detector circuit for use with the probe may include pairs of comparators. Each of the pairs of comparators may have mutually connected inputs with the non-inverting input of one comparator connected to the inverting pair of the other comparator.... | 08/17/1999 |
| 5937310 | Reduced bird's beak field oxidation process using nitrogen implanted into active region A method of forming a self-aligned field oxide isolation structure without using silicon nitride. The method comprises forming a dielectric on an upper surface of a semiconductor substrate. The upper surface of the semiconductor substrate comprises an act... | 08/10/1999 |
| 5926717 | Method of making an integrated circuit with oxidizable trench liner A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a trench in the semiconductor substrate between said first active region and said second ... | 07/20/1999 |
| 5925133 | Integrated processor system adapted for portable personal information devices An integrated processor is fabricated on a single monolithic circuit and employs circuitry to accommodate data-intensive, view-intensive and voice-intensive requirements of modern-day PIDs. The integrated processor includes a CPU core, a memory controller... | 07/20/1999 |
| 5923983 | Integrated circuit gate conductor having a gate dielectric which is substantially resistant to hot carrier effects An integrated circuit is formed whereby transistor gate dielectrics are made less susceptible to hot carrier effects. Barrier atoms are inserted into critical areas to minimize trapping of hot carriers within the gate dielectric. Barrier atoms are incorpo... | 07/13/1999 |
| 5920103 | Asymmetrical transistor having a gate dielectric which is substantially resistant to hot carrier injection A transistor fabrication process is provided which derives a benefit from having an asymmetrical LDD structure. A gate oxide layer is grown across a silicon-based substrate. A polysilicon layer is then deposited across the gate oxide layer. Portions of th... | 07/06/1999 |
| 5914877 | USB based microphone system A powered microphone for use with a personal computer comprising a Universal Serial Bus interface for coupling the powered microphone to a Universal Serial Bus. A circuit coupled to the Universal Serial Bus interface is configured to integrate a plurality... | 06/22/1999 |
| 5909572 | System and method for conditionally moving an operand from a source register to a destination register A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an... | 06/01/1999 |
| 5900666 | Ultra-short transistor fabrication scheme for enhanced reliability A detached drain transistor including a semiconductor substrate, a gate dielectric formed on an upper surface of the substrate, a conductive gate formed on the gate dielectric, a first pair of spacer structures, a first source impurity distribution, a sec... | 05/04/1999 |
| 5899727 | Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The tren... | 05/04/1999 |
| 5891793 | Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation An integrated circuit transistor is provided having a gate oxide and a gate conductor arranged upon a semiconductor topography, the gate oxide and gate conductor are formed within a common chamber. The initial semiconductor topography includes a silicon s... | 04/06/1999 |
| 5863818 | Multilevel transistor fabrication method having an inverted, upper level transistor A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is ... | 01/26/1999 |
| 5861335 | Semiconductor fabrication employing a post-implant anneal within a low temperature high pressure nitrogen ambient to improve channel and gate oxide reliability An integrated circuit is formed with minimal encroachment of lightly doped drain (LDD) implants partially due to barrier atoms incorporated along the migration avenues. Nitrogen is incorporated either during the LDD implant or during an anneal cycle follo... | 01/19/1999 |
| 5851888 | Controlled oxide growth and highly selective etchback technique for forming ultra-thin oxide A method for fabrication a gate dielectric in which an initial dielectric layer comprising a sacrificial portion and a permanent portion is formed on the semiconductor substrate. Thereafter the sacrificial portion is controllably removed with an etchback ... | 12/22/1998 |
| 5849621 | Method and structure for isolating semiconductor devices after transistor formation A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes laterally displaced source/drain regions and channel regions. First and second laterally displaced MOS transistors are formed... | 12/15/1998 |
| 5847462 | Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer An interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided ... | 12/08/1998 |
| 5840610 | Enhanced oxynitride gate dielectrics using NF3 gas A semiconductor manufacturing process in which single crystal silicon substrate is immersed into an oxidation chamber maintained at a first temperature between 400° and 700° C. for a first duration. The oxidation chamber includes a first ambient gas of ... | 11/24/1998 |
