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| Number | Title | Issue Date |
| 6272153 | DVD audio decoder having a central sync-controller architecture An audio decoder architecture makes use of various component sharing techniques to conserve hardware and reduce implementation cost. In one embodiment, the audio decoder comprises a bitstreamer, a synchronization controller, a first and second decode cont... | 08/07/2001 |
| 6225993 | Video on demand applet method and apparatus for inclusion of motion video in multimedia documents A computer process which requests streams of motion video titles and decodes and displays the motion video signals of the stream for display in a computer display device is constructed in the form of an applet of a multimedia document viewer such as a Wor... | 05/01/2001 |
| 5983342 | Superscalar microprocessor employing a future file for storing results into multiportion registers A superscalar microprocessor includes a reorder buffer configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently dispatchable instructions... | 11/09/1999 |
| 5968162 | Microprocessor configured to route instructions of a second instruction set to a second execute unit in response to an escape instruction A microprocessor is provided which detects an escape instruction. The escape instruction indicates that subsequent instructions belong to an alternate instruction set. In one embodiment, the number of subsequent instructions which belong to the alternate ... | 10/19/1999 |
| 5961625 | Bus bridge state monitoring in a bus bridge verification system A system for and a method of monitoring the current state of a bus bridge in a device independent manner are disclosed. In a computer system having a bus bridge connecting a plurality of system buses, a bus bridge model object is created with storage spac... | 10/05/1999 |
| 5956046 | Scene synchronization of multiple computer displays A multi-display video system for ensuring the proper synchronization of scene switching. Before each display switches to pixel data corresponding to the next scene to be rendered, new pixel data is written into a currently unused bank of frame buffer memo... | 09/21/1999 |
| 5944816 | Microprocessor configured to execute multiple threads including interrupt service routines A microprocessor including a context file configured to store multiple contexts is provided. The microprocessor may execute multiple threads, each thread having its own context within the microprocessor. In one embodiment, the present microprocessor is ca... | 08/31/1999 |
| 5916259 | Coaxial waveguide applicator for an electromagnetic wave-activated sorption system The present invention is directed to a coaxial waveguide applicator for an electromagnetic wave-activated sorption system which comprises at least one sorber having a metallic tubular housing defining an outer conductor and first and second ends which are... | 06/29/1999 |
| 5900013 | Dual comparator scheme for detecting a wrap-around condition and generating a cancel signal for removing wrap-around buffer entries A device and method for comparing cancel tags, and for canceling data from a finite wrap-around data buffer. The data buffer stores tag values that are continuous, or sequential. A cancel tag is used to cancel all tags with a value "greater-than" the canc... | 05/04/1999 |
| 5873114 | Integrated processor and memory control unit including refresh queue logic for refreshing DRAM during idle cycles An integrated processor is provided with a memory control unit having refresh queue logic for refreshing dynamic random access memory (DRAM) banks during idle memory cycles. The refresh queue logic includes a queue counter and allows the refresh requests ... | 02/16/1999 |
| 5850555 | System and method for validating interrupts before presentation to a CPU A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a validity checker, and at least one processor interface. The validity c... | 12/15/1998 |
| 5848433 | Way prediction unit and a method for operating the same A way prediction unit for a superscalar microprocessor is provided which predicts the next fetch address as well as the way of the instruction cache that the current fetch address hits in while the instructions associated with the current fetch are being ... | 12/08/1998 |
| 5848254 | Multiprocessing system using an access to a second memory space to initiate software controlled data prefetch into a first address space A computer system defines a write transaction having a certain encoding as a prefetch command. A computer program developed for the computer system may include prefetch commands at points where the program has determined that a previously unreferenced coh... | 12/08/1998 |
| 5842004 | Method and apparatus for decompression of compressed geometric three-dimensional graphics data Three-dimensional compressed geometry is decompressed with a unit having an input FIFO receiving compressed data bits and outputting to an input block state machine and an input block, whose outputs are coupled to a barrel shifter unit. Input block output... | 11/24/1998 |
| 5842041 | Computer system employing a control signal indicative of whether address is within address space of devices on processor local bus An integrated processor is provided that employs an improved address decoding method during bus cycles of an external master. An external PCI master may initiate a cycle (either memory or I/O) on the PCI bus by asserting an address signal on the PCI bus a... | 11/24/1998 |
| 5835165 | Reduction of false locking code words in concatenated decoders A concatenated three layer Viterbi, Reed-Solomon/Deinterleaver and Descrambler forward error correction decoder may be utilized in digital video and audio systems, and for direct broadcast satellite applications. The digital signal may be a compressed vid... | 11/10/1998 |
| 5832440 | Trolling motor with remote-control system having both voice--command and manual modes A device for controlling the speed and direction of a watercraft using voice commands. The device includes a voice recognition computer, which recognizes spoken commands, and a motor control computer which causes the speed and steering direction of the wa... | 11/03/1998 |
| 5828873 | Assembly queue for a floating point unit A microprocessor implements a hierarchical microcode implementation for floating point instructions. Floating point instructions are classified as microcode instructions. The microcode unit parses the floating point instructions into one or more floating ... | 10/27/1998 |
| 5828884 | Method for compiling a software program and executing on a system which converts data between different endian formats A method for compiling a software program and executing the program on a data processing system which performs conversion between data formatted in differing endian formats, namely big-endian and little-endian formats, also known as byte swapping. The dat... | 10/27/1998 |
| 5822558 | Method and apparatus for predecoding variable byte-length instructions within a superscalar microprocessor A superscalar microprocessor is provided that includes a predecode unit configured to predecode variable byte-length instructions prior to their storage within an instruction cache. The predecode unit is configured to generate a plurality of predecode bit... | 10/13/1998 |
| 5822228 | Method for using built in self test to characterize input-to-output delay time of embedded cores and other integrated circuits A system and method for using a BIST generator and a BIST compactor to characterize the propagation delay time of a high-speed embedded cores and integrated circuits in general. In one embodiment, an external clock is provided having a positive edge and a... | 10/13/1998 |
| 5819080 | Microprocessor using an instruction field to specify condition flags for use with branch instructions and a computer system employing the microprocessor A microprocessor is provided including a branch prediction unit configured to select one of multiple sets of condition flags for use by a branch instruction according to the segment register override prefix byte which may be included with the instruction.... | 10/06/1998 |
| 5819059 | Predecode unit adapted for variable byte-length instruction set processors and method of operating the same A superscalar microprocesor is provided that includes a predecode unit adapted for predecoding variable byte-length instructions. The predecode unit predecodes the instructions prior to their storage within an instruction cache. In one system, a predecode... | 10/06/1998 |
| 5819057 | Superscalar microprocessor including an instruction alignment unit with limited dispatch to decode units A high performance superscalar microprocessor including an instruction alignment unit is provided which is capable of routing variable byte length instructions simultaneously to a plurality of decode units which form fixed issue positions within the super... | 10/06/1998 |
| 5819067 | Computer system configured to translate a computer program into a second computer program prior to executing the computer program A computer system is provided which includes at least two microprocessors. The first microprocessor is configured to translate instructions from an original computer program coded in a first instruction set to a translated computer program coded in a seco... | 10/06/1998 |
| 5813035 | Microprocessor employing a technique for restoration of an aborted cycle following a snoop writeback operation A microprocessor is provided with an output pad logic circuit for each of its output lines. Each output pad logic circuit advantageously includes first and second latch circuits each configured to store output information at the same time. When the proces... | 09/22/1998 |
| 5812832 | Digital clock waveform generator and method for generating a clock signal A digital clock waveform generator and method for generating a clock signal are provided for a microprocessor or other digital circuit to provide on chip generation of internal clock signals having the same frequency as or a higher or lower frequency than... | 09/22/1998 |
| 5805839 | Efficient technique for implementing broadcasts on a system of hierarchical buses An architecture for a multiprocessor computer system is provided. The multiprocessor computer system includes multiple repeater nodes. Each repeater node includes a transaction repeater and at least one bus device coupled to the repeater on a lower level ... | 09/08/1998 |
| 5805840 | Bus arbiter employing a transaction grading mechanism to dynamically vary arbitration priority A computer system includes a bus arbiter for controlling the ownership of a bus to which a variety of both real time and non-real time resources are coupled. The bus arbiter includes a request detection unit for detecting bus request signals of a pluralit... | 09/08/1998 |
| 5802563 | Efficient storage of data in computer system with multiple cache levels Memory space in the lower-level cache (LLC) of a computer system is allocated in cache-line sized units, while memory space in the higher-level cache (HLC) of the computer system is allocated in page sized units; with each page including two or more cache... | 09/01/1998 |
| 5802330 | Computer system including a plurality of real time peripheral devices having arbitration control feedback mechanisms A computer system includes a bus arbiter for controlling the ownership of a bus to which a variety of both real time and non-real time resources are coupled. The bus arbiter includes a request detection unit for detecting bus request signals of a pluralit... | 09/01/1998 |
| 5802588 | Load/store unit implementing non-blocking loads for a superscalar microprocessor and method of selecting loads in a non-blocking fashion from a load/store buffer A load/store buffer is provided which allows both load memory operations and store memory operations to be stored within it. Memory operations are selected from the load/store buffer for access to the data cache, including cases where the memory operation... | 09/01/1998 |
| 5802559 | Mechanism for writing back selected doublewords of cached dirty data in an integrated processor An integrated processor is provided that includes a cache controller which keeps track of a physical address in the system memory which corresponds to each entry within the cache memory. The address tag and state logic circuit further contains state infor... | 09/01/1998 |
| 5794846 | Model railroad track alignment apparatus Track alignment apparatus for supporting and linking sections of model railroad track and/or for receiving a model railroad trestle. Track alignment apparatus may include one or more track alignment members to engage trestles, provide rigidity to curved o... | 08/18/1998 |
| 5794028 | Shared branch prediction structure A shared branch prediction mechanism is provided in which a pool of branch prediction storage locations are shared among the multiple cache lines comprising a row of the instruction cache. The branch prediction storage locations within the pool are dynami... | 08/11/1998 |
| 5794010 | Method and apparatus for allowing execution of both compressed instructions and decompressed instructions in a microprocessor A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. ... | 08/11/1998 |
| 5790811 | System and method for performing data transfers during PCI idle clock cycles A computer system and method for performing data transfers during idle PCI clock cycles. The computer system includes a PCI bus, a plurality of devices coupled to the bus, and a bus arbiter coupled to the bus. One of the plurality of devices is a source d... | 08/04/1998 |
| 5790783 | Method and apparatus for upgrading the software lock of microprocessor A method and apparatus for providing, maintaining and upgrading the software lock of a microprocessor. When a processor upgrade occurs, software that was serialized to the previously installed processor detects that it is running on an unauthorized proces... | 08/04/1998 |
| 5790880 | Microprocessor configured to dynamically connect processing elements according to data dependencies A microprocessor is provided which detects dependencies among instructions. The microprocessor assigns each instruction to a processing element or elements which perform the operation specified by the instruction. Additionally, the microprocessor is confi... | 08/04/1998 |
| 5790871 | System and method for testing and debugging a multiprocessing interrupt controller A processing system comprising at least one processing unit, a plurality of I/O devices, and a central interrupt control unit intercoupling the processing unit and the plurality of I/O devices. The central interrupt control unit is configured to receive i... | 08/04/1998 |
