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Vehicular Impact Signaling Device
An apparatus for the deployment of a visible plume to alert other motorists that a proximate motor vehicle has been involved in a collision.
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| Number | Title | Issue Date |
| 7315519 | IPv4/v6 address acquisition techniques for mobile terminals operating within wireless LANs Disclosed herein are techniques by which a Layer-2 entity determines whether a mobile terminal requesting association or reassociation therewith determines whether the requesting mobile terminal shall continue using its current IP address or whether it requires a ne... | 01/01/2008 |
| 6912217 | Protocol stack encapsulation for voice processor A system and method are presented for the encapsulation of a protocol stack in a voice telephony processor. Utilizing the system and method disclosed herein, digital voice telephony signals received in TDM frame-based format are converted to packet-based or cell-bas... | 06/28/2005 |
| 6854082 | Unequal error protection Reed-Muller code generator and decoder An unequal error protection Reed-Muller code and method for designing a generator matrix and decoder. A conventional RM code is concatenated with the combination of itself and a subcode of itself. The new generator matrix is decomposed to include empty submatrices. ... | 02/08/2005 |
| 6810460 | AMBA bus off-chip bridge An application specific integrated circuit, ASIC, having an advanced high-speed bus, AHB, operating in Advanced Microcontroller Bus Architecture, AMBA, and a bridge for connecting to an off-chip device is disclosed. The bridge includes a logical section and a buffer... | 10/26/2004 |
| 6691264 | Built-in self-repair wrapper methodology, design flow and design architecture A "Wrapper" system and method are presented for integrating built-in self-test (BIST) and built-in self-repair (BISR) functions in a semiconductor memory device. The wrapper reduces the usual dependency of BISR circuitry on the BIST design, so that modifi... | 02/10/2004 |
| 6687773 | Bridge for coupling digital signal processor to on-chip bus as master A bridge for connecting a DSP to an ASIC on-chip bus as a master on the bus. The bridge includes a DSP instruction unit master interface and a DSP data unit master interface to convert DSP instruction unit and data unit external signals into bus protocol ... | 02/03/2004 |
| 6673708 | Thermal and mechanical attachment of a heatspreader to a flip-chip integrated circuit structure using underfill An integrated circuit structure and a method for packaging an integrated circuit are described. The integrated structure includes an integrated circuit that is inverted and solder bump mounted to a substrate. An underfill is used to encapsulate the solder... | 01/06/2004 |
| 6665355 | Method and apparatus for pilot-aided carrier acquisition of vestigial sideband signal An inexpensive synchronous detection module is disclosed for a sideband signal receiver that provides for flexibility in design of the tuner. The detection module is adaptable to detection of upper or lower sideband signals. One embodiment includes an ana... | 12/16/2003 |
| 6650139 | Modular collection of spare gates for use in hierarchical integrated circuit design process A system and method are presented for using spare gates to repair logic errors in a digital logic IC with a hierarchical physical design. According to the system and method, the spare gates are organized as scalable modules, consisting of varying numbers ... | 11/18/2003 |
| 6643204 | Self-time scheme to reduce cycle time for memories A self-time circuit and method are presented for reducing the write cycle time in a semiconductor memory. A "dummy" memory cell having the same timing requirements as the functional cells, and associated write logic are added to the standard circuitry of ... | 11/04/2003 |
| 6640321 | Built-in self-repair of semiconductor memory with redundant row testing using background pattern A method is presented for self-test and self-repair of a semiconductor memory device. Prior to the self-repair stage, both redundant and regular memory portions are comprehensively tested, preferably using a checkerboard bit pattern. Faulty rows identifie... | 10/28/2003 |
| 6633969 | Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions An apparatus and method for translating variable-length instructions to fixed-length instructions. The apparatus includes instruction decompression logic and caching logic. The instruction decompression logic receives a first portion of an instruction dat... | 10/14/2003 |
| 6629309 | Mask-programmable ROM cell A structure for programming a memory cell on an integrated circuit provides access at multiple mask levels of the integrated circuit to each of the programming voltages which may be used to program the memory cell. In an embodiment, the structure includes... | 09/30/2003 |
| 6623992 | System and method for determining a subthreshold leakage test limit of an integrated circuit A method and a means for determining an IDDQ test limit of an integrated circuit are provided. In particular, a method is provided which includes measuring the IDDQ value of a test structure formed upon a die derived from the same lo... | 09/23/2003 |
| 6608376 | Integrated circuit package substrate with high density routing mechanism An integrated circuit package is provided that allows high density routing of signal lines. A substrate of the package may include an upper surface upon which a bonding finger resides, a lower surface upon which a solder ball resides, and a signal conduct... | 08/19/2003 |
| 6606007 | Crystal oscillator with minimized Q reduction A circuit and method are disclosed herein for a crystal oscillator, wherein the Q of the resonant network is not reduced through the loading effects of the oscillator's resistive bias network. The oscillator is configured as an operational transconductanc... | 08/12/2003 |
| 6594741 | Versatile write buffer for a microprocessor and method using same A system and method are presented for a write buffer that combines capabilities and features implemented in separate, specialized buffers in prior art microprocessors. The write buffer receives data records from a CPU and subsequently transfers them to a ... | 07/15/2003 |
| 6590409 | Systems and methods for package defect detection A charged particle imaging system may be used to perform package-level failure analysis by providing a Capacitive Coupling Voltage Contrast image of a portion of the semiconductor package. Preliminary failure analysis using Time Domain Reflectometry may d... | 07/08/2003 |
| 6590292 | Thermal and mechanical attachment of a heatspreader to a flip-chip integrated circuit structure using underfill An integrated circuit structure and a method for packaging an integrated circuit are described. The integrated structure includes an integrated circuit that is inverted and solder bump mounted to a substrate. An underfill is used to encapsulate the solder... | 07/08/2003 |
| 6587390 | Memory controller for handling data transfers which exceed the page width of DDR SDRAM devices A memory controller includes a pair of input command decoders and a pair of multiplexers. If the memory controller receives a data transfer request related to a read or write burst which will stay within a page of memory, the first input command decoder c... | 07/01/2003 |
| 6573113 | Integrated circuit having dedicated probe pads for use in testing densely patterned bonding pads An integrated circuit topography is provided which includes at least two rows of bonding pads. Each row of bonding pads is attributed a row of probe pads. One row of probe pads is contained within the scribe area and suffices as a sacrificial row of probe... | 06/03/2003 |
| 6574762 | Use of a scan chain for configuration of BIST unit operation An integrated circuit device is disclosed having a boundary scan chain and a hardwired BIST unit that is configurable via the control circuitry for the boundary scan chain. In one embodiment, the device includes application logic, a BIST unit, a boundary ... | 06/03/2003 |
| 6570626 | On-screen display format reduces memory bandwidth for on-screen display systems A video system is disclosed that processes OSD images and displays the OSD images on a display. At least some of the OSD images are represented by data sets that do not include a color palette. Each OSD data set includes a header comprising multiple bits ... | 05/27/2003 |
| 6564313 | System and method for efficient instruction prefetching based on loop periods The invention contemplates a system and method for efficient instruction prefetching based on the termination of loops. A computer system may be contemplated herein, wherein the computer system may include a semiconductor memory device, a cache memory dev... | 05/13/2003 |
| 6559088 | Ziegler-Natta catalyst with amine for polymerization Provided is a catalyst system for polymerization of monomer having at least one Ziegler-Natta polymerizable bond comprising: c) a supported Ziegler-Natta transition metal catalyst component comprising a Group 15 atom having two groups selected from the group c... | 05/06/2003 |
| 6550032 | Detecting interport faults in multiport static memories A multiport testing procedure capable of detecting faults that occur between static random access memory ports as well as traditional cells faults uncovers all possible faults and covers all cells in the memory, without placing architectural constraints o... | 04/15/2003 |
| 6540467 | Apparatus and method of semiconductor wafer protection A system and a method are provided for preventing damage to wafers arranged in a wafer cassette. In particular, an apparatus is provided to protect wafers arranged in a wafer cassette during insertion of a wafer into the cassette. In one embodiment, the a... | 04/01/2003 |
| 6531553 | Process for increasing molecular weight in polyolefins using Ziegler-Natta catalysts and lithium compounds This invention relates to a conventional supported heterogeneous Ziegler-Natta catalyst for the polymerization of olefins. It has been found that adding a lithium compound to a transition metal catalyst component and then adding an organoaluminum co-catal... | 03/11/2003 |
| 6532585 | Method and apparatus for application of proximity correction with relative segmentation The present invention is a method and apparatus for applying one-dimensional proximity correction to a piece of a mask pattern, by segmenting a first piece of a mask pattern with horizontal dividing lines into a plurality of segments, segmenting a second ... | 03/11/2003 |
| 6526637 | Device for continuous production of foil expanded metal A device for continuous production of foil expanded metal comprising a cutting unit for continuous production of parallel, staggered longitudinal cuts in the foil, and an expansion unit for expanding the foil with the cuts perpendicularly to the longitudi... | 03/04/2003 |
| 6507672 | Video encoder for digital video displays An improved multimedia encoder having features advantageous for use in a computer system. These features provide for the reduction of bandwidth and storage requirements, the enhancement of noise immunity, the evening of computational loading, and the use ... | 01/14/2003 |
| 6505308 | Fast built-in self-repair circuit A fast method and apparatus for built-in self-repair (BISR) of memory arrays is disclosed. In one embodiment, an integrated circuit includes a repair circuit coupled between the address decoder and the memory array. The address decoder receives memory add... | 01/07/2003 |
| 6505313 | Multi-condition BISR test mode for memories with redundancy A memory device configured to detect changes in fault patterns is disclosed. In one embodiment, the memory device includes a memory array, a built-in self-test (BIST) unit, and a built-in self-repair (BISR) unit. The BIST unit runs test patterns on the me... | 01/07/2003 |
| 6496950 | Testing content addressable static memories A CAM testing procedure detects storage logic faults, comparison logic faults, and faults caused by interactions between the storage and comparison logic for both single port and dual port CAM's. To uncover faults in the storage logic, a series of read an... | 12/17/2002 |
| 6493506 | Optical disk system and method for storing disk- and user-specific settings An optical disk system is presented which stores disk- and user-specific settings, along with an associated method. The optical disk system includes a disk drive unit for retrieving identification data and encoded video data stored upon an optical disk, a... | 12/10/2002 |
| 6488907 | Catalytic partial oxidation processes and catalysts with diffusion barrier coating A process for the production of synthesis gas from light hydrocarbons such as methane includes the net catalytic partial oxidation of a hydrocarbon feedstock by contacting a feed stream comprising the hydrocarbon feedstock and an O2 -containing... | 12/03/2002 |
| 6489378 | Method for the preparation of core-shell morphologies from polybutadiene-polystyrene graft copolymers High impact polystyrene having a predominant core-shell morphology is made by polymerizing styrene in the presence of polybutadiene using toluene as a solvent. The thermoplastic polymer composition is characterized by a continuous phase of polystyrene con... | 12/03/2002 |
| 6486220 | Regeneration procedure for Fischer-Tropsch catalyst A process is disclosed for regenerating catalyst used in a process for synthesizing hydrocarbons. The synthesis process involves contacting a feed stream comprising hydrogen and carbon monoxide with a catalyst in a reaction zone maintained at conversion-p... | 11/26/2002 |
| 6483754 | Self-time scheme to reduce cycle time for memories A self-time circuit and method are presented for reducing the write cycle time in semiconductor memory. A "dummy" memory cell having the same timing requirements as the functional cells, and associated write logic are added to the standard circuitry of th... | 11/19/2002 |
| 6483951 | Digital video filter sequence for bandwidth constrained systems A video filter unit is described which is implemented as a three-stage filter comprising a vertical filter, a horizontal decimation filter, and a horizontal interpolation filter. The three stages of the filter unit preferably connect serially with the ver... | 11/19/2002 |
