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| Number | Title | Issue Date |
| 5703826 | Video random access memory chip configured to transfer data in response to an internal write signal The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the ... | 12/30/1997 |
| 5699314 | Video random access memory device and method implementing independent two we nibble control The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the ... | 12/16/1997 |
| 5696014 | Method for increasing capacitance of an HSG rugged capacitor using a phosphine rich oxidation and subsequent wet etch A capacitor and method for forming the capacitor having HSG polysilicon with reduced dielectric bridging, increased capacitance, and minimal depletion effects. A first polysilicon layer is deposited and doped with impurities to increase conductivity. A se... | 12/09/1997 |
| 5691235 | Method of depositing tungsten nitride using a source gas comprising silicon A method for depositing tungsten nitride uses a source gas mixture having a silicon based gas, such as silane for depositing the tungsten nitride to overlie a deposition substrate. A non-planar storage capacitor has a tungsten nitride capacitor electrode.... | 11/25/1997 |
| 5691211 | Method for gettering noble metals from mineral acid solution Silicon is employed as a reducing agent in an acid bath to adsorb noble metals present as contaminants in the acid. In the manufacture of silicon devices for electronic memory and other devices, polonium-210 is adsorbed by silicon getters to reduce soft e... | 11/25/1997 |
| 5658391 | Method of chamber cleaning in MOCVD application The invention is a process for cleaning a chamber after a chemical vapor deposition has been performed therein. A residue formed during the deposition is combined with a reactive species to form a gas containing an organic substance once found in the resi... | 08/19/1997 |
| 5650976 | Dual strobed negative pumped wordlines for dynamic random access memories The invention is a circuit and a method for resetting a wordline by driving a potential of the wordline toward a ground reference potential prior to driving the potential of the wordline to a negative potential.... | 07/22/1997 |
| 5612657 | Inherently impedance matched integrated circuit socket A socket having primary conductors and secondary conductors. The socket provides electrical connection between active circuitry installed on a substrate and external circuitry. The impedance between each primary conductor and each secondary conductor is a... | 03/18/1997 |
| 5599396 | High density inductively and capacitively coupled plasma chamber An inductively coupled plasma chamber having a capacitor electrode during cleaning of the plasma chamber.... | 02/04/1997 |
| 5594474 | VRAM having isolated array sections for providing write functions that will not affect other array sections A video RAM having isolated array sections for providing write function that will not affect other array sections. The whole VRAM memory array does not have to be completely read before writing new pixel information to particular array section. At least t... | 01/14/1997 |
| 5574698 | Ram row decode circuitry that utilizes a precharge circuit that is deactivated by a feedback from an activated word line driver A precharge circuit which is deactivated once a word line driver is activated. Specifically, a low output signal created by the selected driver is fed back to the precharge circuit to deactivate the precharge circuit during activation of a chosen word lin... | 11/12/1996 |
| 5573837 | Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming narrow isolated trenches defined by said masking layer An etch mask having a narrow spacer layer self-aligned and adjacent to a first portion of an inorganic first layered segment. An inorganic second layered segment comprises a portion of the etch mask and encompasses a perimeter of the first layered segment... | 11/12/1996 |
| 5555429 | Multiport RAM based multiprocessor Presented is an integrated circuit chip including a random access memory (RAM) array, serial access memory (SAM), an arithmetic logic unit, a bidirectional shift register, and masking circuitry. The arithmetic logic unit, SAM, shift register, and masking ... | 09/10/1996 |
| 5544108 | Circuit and method for decreasing the cell margin during a test mode The invention is a monolithic memory device having a circuit and a method for decreasing the cell margin during a test mode. Decreasing the cell margin stresses the memory device during the test mode greater than a stress experienced during normal operati... | 08/06/1996 |
| 5537306 | Low voltage charge pump circuit and method for pumping a node to an electrical potential A charge pump circuit and method for increasing a value of a supply potential. The charge pump circuit features a first stage circuit for generating an intermediate pumped potential greater than an input supply potential. The intermediate pumped potential... | 07/16/1996 |
| 5528603 | Apparatus and method for testing an integrated circuit using a voltage reference potential and a reference integrated circuit An integrated circuit testing apparatus and method of testing. In a first embodiment an amplifier amplifies the difference in a reference integrated circuit (RIC) response and a device under test integrated circuit (DUTIC) response to an electrical stimul... | 06/18/1996 |
| 5523261 | Method of cleaning high density inductively coupled plasma chamber using capacitive coupling An inductively coupled plasma chamber having a capacitor electrode during cleaning of the plasma chamber.... | 06/04/1996 |
| 5501767 | Method for gettering noble metals from mineral acid solution Silicon is employed as a reducing agent in an acid bath to adsorb noble metals present as contaminants in the acid. In the manufacture of silicon devices for electronic memory and other devices, polonium-210 is adsorbed by silicon getters to reduce soft e... | 03/26/1996 |
| 5500817 | True tristate output buffer and a method for driving a potential of an output pad to three distinct conditions The invention is a circuit and method for providing a true tristate output at an output pad of a serial access memory device. The invention drives three distinct potentials to the output pad, two of which are potentials having high and low logic levels. T... | 03/19/1996 |
| 5478772 | Method for forming a storage cell capacitor compatible with high dielectric constant materials The invention is a storage cell capacitor having a storage node electrode comprising a barrier layer interposed between a conductive plug and an oxidation resistant layer. A thick insulative layer protects the sidewalls of the barrier layer during the dep... | 12/26/1995 |
| 5475631 | Multiport RAM based multiprocessor Presented is an integrated circuit chip including a random access memory (RAM) array, serial access memory (SAM), an arithmetic logic unit, a bidirectional shift register, and masking circuitry. The arithmetic logic unit, SAM, shift register, and masking ... | 12/12/1995 |
| 5469393 | Circuit and method for decreasing the cell margin during a test mode The invention is a monolithic memory device having a circuit and a method for decreasing the cell margin during a test mode. Decreasing the cell margin stresses the memory device during the test mode greater than a stress experienced during normal operati... | 11/21/1995 |
| 5464031 | Method of chamber cleaning in MOCVD applications The invention is a process for cleaning a chamber after a chemical vapor deposition has been performed therein. A residue formed during the deposition is combined with a reactive species to form a gas containing an organic substance once found in the resi... | 11/07/1995 |
| 5455801 | Circuit having a control array of memory cells and a current source and a method for generating a self-refresh timing signal A method and circuit for generating a self-refresh mode signal and a self-refresh cycle signal. The circuit is a dynamic random access memory (DRAM) device having a control array of control cells charged to a potential by a current source and having a mon... | 10/03/1995 |
| 5420061 | Method for improving latchup immunity in a dual-polysilicon gate process The invention is a method for creating a portion of an integrated circuit on a semiconductor wafer. The invention comprises doping a substrate to form a doped well region having an opposite conductivity type than the substrate. Separate photomasking steps... | 05/30/1995 |
| 5410508 | Pumped wordlines The invention is a circuit and method for maintaining a negative potential, with respect to the digit line potential, on non-selected wordlines.... | 04/25/1995 |
| 5400289 | Lockout circuit and method for preventing metastability during the termination of a refresh mode A circuit and method for preventing glitches from occurring during a termination of a self-refresh mode when a race condition exits between an external row address strobe signal* (RAS*) transitioning to an inactive state and an internally generated self-r... | 03/21/1995 |
| 5400283 | RAM row decode circuitry that utilizes a precharge circuit that is deactivated by a feedback from an activated word line driver There is a precharge circuitry that uses little real estate and can be deactivated once a word line driver is activated. Specifically, a high signal created by the selected driver is fed back to the precharge circuit to deactivate it when activating a cho... | 03/21/1995 |
| 5400003 | Inherently impedance matched integrated circuit module A semiconductor circuit module is formed with external connections on coaxial pins. This provides a controlled impedance between a ground connection and a signal connection which is substantially equal per unit length. The module may be configured so that... | 03/21/1995 |
| 5394320 | Low voltage charge pump circuit and method for pumping a node to an electrical potential A charge pump circuit and method for increasing a value of a supply potential. The charge pump circuit features a first stage circuit for generating an intermediate pumped potential greater than an input supply potential. The intermediate pumped potential... | 02/28/1995 |
| 5394172 | VRAM having isolated array sections for providing write functions that will not affect other array sections A video RAM having isolated array sections for providing write function that will not affect other array sections. The whole VRAM memory array does not have to be completely read before writing new pixel information to particular array section. At least t... | 02/28/1995 |
| 5393564 | High efficiency method for performing a chemical vapor deposition utilizing a nonvolatile precursor The invention is a method directed to the use of a nonvolatile precursor, either a solid precursor or a liquid precursor, suitable for chemical vapor deposition (CVD), including liquid source CVD (LSCVD), of a semiconductor film. Using the method of the i... | 02/28/1995 |
| 5392189 | Capacitor compatible with high dielectric constant materials having two independent insulative layers and the method for forming same The invention is a storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode comprising a barrier layer interposed between a conductive plug and an oxidation resistant layer. A thick insulative layer protec... | 02/21/1995 |
| 5387315 | Process for deposition and etching of copper in multi-layer structures An integral process is provided for depositing onto, and etching a layer of copper from, a multi-layer structure. The subject process, which is conducted within a vacuum chamber, comprises providing a multi-layer having at least one major surface in which... | 02/07/1995 |
| 5385629 | After etch test method and apparatus There is a post etching test apparatus and method to be able to only test just a few die on the wafer. Uniquely, the remainder of the die on the wafer can be salvaged, if the test identifies proper tolerances for the etching process over the entire wafer ... | 01/31/1995 |
| 5381302 | Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same The invention is a storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode comprising a barrier layer interposed between a conductive plug and an oxidation resistant layer. A layer of titanium silicide is... | 01/10/1995 |
| 5378641 | Electrically conductive substrate interconnect continuity region and method of forming same with an angled implant The invention is a semiconductor memory structure having an electrically conductive substrate interconnect formed to provide electrical continuity between a buried contact region and a source/drain region of a transistor without overlap of the buried cont... | 01/03/1995 |
| 5369317 | Circuit and method for controlling the potential of a digit line and in limiting said potential to a maximum value The invention is a circuit and method for controlling a high potential at a significant node by controlling the potential at a control input to an electrical device in electrical communication with the significant node. The potential of the control input ... | 11/29/1994 |
| 5349247 | Enhancement circuit and method for ensuring diactuation of a switching device An output driver circuit of a DRAM is wired in a push-pull arrangement. A CMOS transistor arrangement provides a strong output signal. This transistor arrangement comprises the pull-up transistor circuit of the push-pull arrangement. A bootstrap circuit g... | 09/20/1994 |
| 5335201 | Method for providing synchronous refresh cycles in self-refreshing interruptable DRAMs The invention is a method for synchronizing the refresh cycles of a bank of self-refreshing interruptable DRAMs. The refresh cycles are synchronized through a bidirectional control path from each self-refreshing interruptable DRAM to its respective extern... | 08/02/1994 |
