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| Number | Title | Issue Date |
| 8128749 | Fabrication of SOI with gettering layer An SOI substrate has a gettering layer of silicon-germanium (SiGe) with 5-10% Ge, and a thickness of approximately 50-1000 nm. Carbon (C) may be added to SiGe to stabilize the dislocation network. The SOI substrate may be a SIMOX SOI substrate, or a bonded SOI subst... | 03/06/2012 |
| 8084788 | Method of forming source and drain of a field-effect-transistor and structure thereof A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication pro... | 12/27/2011 |
| 8039837 | In-line voltage contrast detection of PFET silicide encroachment A semiconductor test structure includes a PFET transistor, having a source region, a drain region, a gate disposed between the source region and the drain region, a body disposed under the gate, and a body contact. The source region and drain region float, and the b... | 10/18/2011 |
| 8008209 | Thermal gradient control of high aspect ratio etching and deposition processes A technique is described whereby temperature gradients are created within a semiconductor wafer. Temperature sensitive etching and/or deposition processes are then employed. These temperature sensitive processes proceed at different rates in regions with different t... | 08/30/2011 |
| 7795914 | Circuit design methodology to reduce leakage power A three stage circuit according to the invention comprises a data input, a data output, a control input, two voltage supply inputs. The first stage is electrically connected to the data input and control input and is defined by a combinatorial circuitry with two out... | 09/14/2010 |
| 7749903 | Gate patterning scheme with self aligned independent gate etch A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. ... | 07/06/2010 |
| 7612270 | Nanoelectromechanical digital inverter A digital inverter formed by three carbon nanotubes (CNTs) extending vertically from a substrate, one CNT functioning as first source (S1) and having a first logic signal applied to it, another CNT functioning as second source (S2) and having a second ... | 11/03/2009 |
| 7538029 | Method of room temperature growth of SiOon silicide as an etch stop layer for metal contact open of semiconductor devices Silicide is protected during MC RIE etch by first forming an oxide film over the silicide and, after performing MC RIE etch, etching the oxide film. The oxide film is formed from a film of alloyed metal-silicon (M-Si) on the layer of silicide, then wet etching the m... | 05/26/2009 |
| 7531401 | Method for improved fabrication of a semiconductor using a stress proximity technique process An improved method for applying stress proximity technique process on a semiconductor device and the improved device is disclosed. In one embodiment, the method utilizes an additional set of sidewall spacers on one or more NFET devices during the fabrication process... | 05/12/2009 |
| 7510463 | Extended life conditioning disk The present invention is an apparatus and method for extending the life of abrasive disks used in the conditioning of polishing pads used in chemical mechanical planarization (CMP) of polishing pads used to polish and/or planarize the surfaces of semiconductor wafer... | 03/31/2009 |
| 7509186 | Method and system for reducing the variation in film thickness on a plurality of semiconductor wafers having multiple deposition paths in a semiconductor manufacturing process A method and system for reducing the variation in film thickness on a plurality of semiconductor wafers having multiple deposition paths in a semiconductor manufacturing process is disclosed. A film of a varying input thickness is applied to semiconductor wafers mov... | 03/24/2009 |
| 7482282 | Use of dilute hydrochloric acid in advanced interconnect contact clean in nickel semiconductor technologies A method for cleaning oxide from the interconnects of a semiconductor that are comprised of nickel (Ni) silicide or nickel-silicide alloys where nickel is the primary metallic component is disclosed. The cleaning comprises performing an SC1 cycle, exposing the wafer... | 01/27/2009 |
| 7482270 | Fully and uniformly silicided gate structure and method for forming same Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysil... | 01/27/2009 |
| 7359768 | Route input system A software-enabled Route Input System (RIS) process facilitates consistent communication among the various entities involved in route creation, where the entities have different tasks and objectives. The primary teams are the process flow definers (IE), individual p... | 04/15/2008 |
| 7270269 | Secure electronic voting device A secure device for electronic voting employs a write-once vote-recording medium. The medium has an initial writing mode in which data can be written but not read and a subsequent reading mode whereby data can be read but writing is permanently disabled. Once switch... | 09/18/2007 |
