Quotables
"That’s an amazing invention, but who would ever want to use one of them?"
President Rutherford B. Hayes ; Said in 1876, after Alexander Graham Bell demonstrated the telephone to him at the White House
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8015361 | Memory-centric page table walker The page table walker is moved from its conventional location in the memory management unit associated with the data processor to a location in main memory i.e. the main memory controller. As a result, an implementation is provided wherein the processing of requests... | 09/06/2011 |
| 8006244 | Controller for multiple instruction thread processors A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then ba... | 08/23/2011 |
| 7984038 | Longest prefix match (LPM) algorithm implementation for a network processor Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exac... | 07/19/2011 |
| 7788636 | System and method for deriving stochastic performance evaluation model from annotated UML design model The computer program enables a computer to function as: means for transforming a static call graph into a syntax tree having a binary tree structure; means for transforming a protocol state diagram into a stochastic process algebraic form; means for transforming an ... | 08/31/2010 |
| 7486127 | Transistor switch with integral body connection to prevent latchup A circuit device having a transistor-based switch topology that substantially eliminates the possibility of latchup of the device. A series-connected low voltage threshold (LVT) N-channel transistor and a pull-up resistor are coupled across a switching (P-channel) t... | 02/03/2009 |
| 7483913 | XML-based system and method for collaborative web-based design and verification of system-on-a-chip A computer-based design framework for collaborative design of a product by distributed design team members. The design framework comprises: a virtual database management system, which receives data from a plurality of distinct sources and creates a single relational... | 01/27/2009 |
| 7474132 | Automatic self-adaptive keeper system with current sensor for real-time/online compensation for leakage current variations A device and method for automatically detecting and optimally compensating die leakage current under a wide range of leakage conditions. A variable or reconfigurable (self-adaptive) keeper tracks current leakage online (in real time). The control input to the keeper... | 01/06/2009 |
| 7466687 | Packet classification using modified range labels A method and system for encoding a set of range labels for each parameter field in a packet classification key in such a way as to require preferably only a single entry per rule in a final processing stage of a packet classifier. Multiple rules are sorted accorded ... | 12/16/2008 |
| 7461379 | Inter process communications in a distributed CP and NP environment A lightweight, low cost solution provides inter process communications (IPC) in a network processing environment. A method of inter process communication (IPC) between General Purpose Processors in a network processing environment uses software based functions (Appl... | 12/02/2008 |
| 7428677 | Boundary scan apparatus and interconnect test method An electronic device, such as chip, card, system and in situ boundary scan test facilities are disclosed. The boundary scan test facility includes a boundary scan cell (Level Sensitive Scan Design, LSSD structure and selector) connected between output pads of the el... | 09/23/2008 |
| 7417416 | Regulator with load tracking bias An electrical circuit that provides accurate, regulated output voltage over a wide range of input voltages, while exhibiting each of three desired characteristics: accuracy across different supply/process/temperature; stability and linearity yielding phase/gain marg... | 08/26/2008 |
| 7417469 | Compensation for leakage current from dynamic storage node variation by the utilization of an automatic self-adaptive keeper A method and system for automatically detecting and optimally compensating a wide range of die leakage currents in dynamic circuits is presented. A self-adaptive keeper tracks the leakage and reduces the leakage effects by optimally controlled compensation current. ... | 08/26/2008 |
| 7403536 | Method and system for resequencing data packets switched through a parallel packet switch A method to resequence packets includes sequentially allocating in each source ingress adapter a packet rank to each packet received within each source ingress adapter. In each destination egress adapter, each ranked data packet is stored at a respective buffer addr... | 07/22/2008 |
| 7391187 | Regulator with load tracking bias An electrical circuit that provides accurate, regulated output voltage over a wide range of input voltages, while exhibiting each of three desired characteristics: accuracy across different supply/process/temperature; stability and linearity yielding phase/gain marg... | 06/24/2008 |
| 7368902 | Impedance calibration for source series terminated serial link transmitter Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors eac... | 05/06/2008 |
| 7332932 | Serial link receiver with wide input voltage range and tolerance to high power voltage supply A circuit device and method for designing a serial link receiver, which accommodates a wide input voltage range and provides tolerance to high termination voltages. The receiver is designed with a pair of RC networks connected inline between the input and the preamp... | 02/19/2008 |
| 7315901 | Method and system for network processor scheduling outputs using disconnect/reconnect flow queues A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress... | 01/01/2008 |
| 7307447 | Self series terminated serial link transmitter having segmentation for amplitude, pre-emphasis, and slew rate control and voltage regulation for amplitude accuracy and high voltage protection A circuit design method and transmitter that enables flexible control of amplitude, pre-emphasis, and slew rate utilizing a design of a segmented self-series terminated (SSST) transmitter having a parallel configuration of multiple, individually controllable segment... | 12/11/2007 |
| 7268613 | Transistor switch with integral body connection to prevent latchup A circuit device having a transistor-based switch topology that substantially eliminates the possibility of latchup of the device. A series-connected low voltage threshold (LVT) N-channel transistor and a pull-up resistor are coupled across a switching (P-channel) t... | 09/11/2007 |
| 7143414 | Method and apparatus for locking multiple semaphores Processor threads in a multi-processor system can concurrently lock multiple semaphores by providing a lock command which includes the semaphore value and a semaphore number. Each processor is allocated two or more addressable semaphore stores, each of which include... | 11/28/2006 |
| 7032146 | Boundary scan apparatus and interconnect test method An electronic device, such as chip, card, system and in situ boundary scan test facilities are disclosed. The boundary scan test facility includes a boundary scan cell (Level Sensitive Scan Design, LSSD structure and selector) connected between output pads of the el... | 04/18/2006 |
| 6981027 | Method and system for memory management in a network processing system A method and system for memory management in a network processing system provides for allocation of physical memory areas within network processors coupled to a control point processor by a bus. The allocation scheme provides a memory management layer without requir... | 12/27/2005 |
| 6972962 | Expansion board apparatus and removing method In part, and in addition to apparatus and methods presented, an expansion board to be connected/disconnected to/from its mother board easily is provided. A face of a CDC (Communication Daughter Card), which is an expansion board to be connected to the mother board o... | 12/06/2005 |
| 6965922 | Computer system and method with internal use of networking switching A computer system in which a network processor disposed between a central processing unit and supporting peripheral subsystems and among the peripheral subsystems handles addressing of memory space. ... | 11/15/2005 |
| 6880158 | Network processor services architecture that is platform and operating system independent A system for providing a scalable processor and operating system independent network processor services architecture. The system includes a plurality of portable and individualized functional components representing particular segments of the control processor's dev... | 04/12/2005 |
