Bizarre Patents
Combination Beverage Container and Spittoon
A combination beverage container and spittoon includes a bottom portion including outer wall and a first inner wall defining a spittoon space.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8195705 | Hybrid search memory for network processor and computer systems A system includes a data structure having a Direct Table (DT), Patricia-Trees, Pointers and high speed storage systems such as Contents Address Memory (CAM). The DT has a plurality of entries with each one coupled to a Patricia Tree having multiple nodes coupled to ... | 06/05/2012 |
| 8139594 | Apparatus and method to coordinate calendar searches in a network scheduler given limited resources A system that indicates which frame should next be removed by a scheduler from flow queues within a network device, such as a router, network processor, and like devices is disclosed. The system includes a search engine that searches a set of calendars under the con... | 03/20/2012 |
| 8132134 | Closed-loop 1×N VLSI design system Embodiments that design integrated circuits using a closed loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may com... | 03/06/2012 |
| 8055984 | Forward error correction scheme compatible with the bit error spreading of a scrambler A method for combining a simple forward error correction code i.e., a Hamming-like code with scrambling and descrambling functions is disclosed. Therefore, irrespective of the information to be transported, received data may be corrected, bit error spreading effects... | 11/08/2011 |
| 7962848 | Method and system for reducing the horizontal space required for displaying a column containing text data A method and system for reducing an amount of horizontal space required when displaying a plurality of columns on a display screen is disclosed. The at least one column of the plurality of columns has at least one entry containing text data. The method and system in... | 06/14/2011 |
| 7839797 | Event-driven flow control for a very high-speed switching node A method for controlling the flows of data packets that are switched or routed at nodes of high-speed communication networks is disclosed. According to the invention, resource metering units are assigned to resources shared between devices of the switch or router e.... | 11/23/2010 |
| 7826476 | Apparatus and method to reserve resources in communications system A Resource Reservation System includes a Token Generation Unit (TGU) which generates and circulates among nodes of a communications system a Slotted Token (SLT) message having sub-fields to carry identification number for each input port in a node and the resource a... | 11/02/2010 |
| 7779235 | Using performance data for instruction thread direction A method for dispatching instructions in the data processing system, having in memory for storing instructions and a plurality of central processing units, where each central processing unit includes a circuit to provide data indicating internal performance, the met... | 08/17/2010 |
| 7768315 | Multiplexor with leakage power regulator A circuit for a multiplexer includes a pair of NAND gates with outputs coupled to an OAI gate constructed from a complementary circuit formed from solid state devices. A current flow controller formed from solid state devices is coupled to one of the NAND gates. Whe... | 08/03/2010 |
| 7730282 | Method and apparatus for avoiding data dependency hazards in a microprocessor pipeline architecture using a multi-bit age vector A method and system for avoiding various hazards for instructions which are propagating through a microprocessor pipeline. When a plurality of instructions exist within the pipeline which read and write the same value, a vector is established to distinguish the olde... | 06/01/2010 |
| 7714635 | Digital adaptive voltage supply Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. These measurement circuits include registers that are connected to a voltage regulation circuit that provides the integrated circuit voltage source and to a... | 05/11/2010 |
| 7712003 | Methodology and system to set JTAG interface A method and apparatus determines and sets operating voltage on a JTAG interface by incrementally increasing a test voltage applied thereto. The contents of a register is monitored to detect when the contents switch (change) from a first value to a second value. The... | 05/04/2010 |
| 7711930 | Apparatus and method for decreasing the latency between instruction cache and a pipeline processor A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an inter... | 05/04/2010 |
| 7671678 | Serial link output stage differential amplifier and method Protection for the transmission of higher amplitude outputs required of differential amplifiers formed by thin oxide transistors with limited maximum voltage tolerance used where compliance with communication protocol standards requires handling voltages which may, ... | 03/02/2010 |
| 7644233 | Apparatus and method for supporting simultaneous storage of trace and standard cache lines A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. A mechanism is described for indexing into the cache, and se... | 01/05/2010 |
| 7620048 | Network switch and components and method of operation An apparatus is disclosed for transporting control information in a communications system. The apparatus comprises a network processor, a control point processor operatively coupled to the network processor, and a guided frame generated by the control point processo... | 11/17/2009 |
| 7610449 | Apparatus and method for saving power in a trace cache A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Power is conserved by guiding access to lines stored in the ... | 10/27/2009 |
| 7590057 | Network switch and components and method of operation A control sub system, a plurality of interface processors, a plurality of media interfaces a plurality of queues are operatively coupled and responsive to a control signal to move data from a memory to a selected one of the plurality of queues. ... | 09/15/2009 |
| 7560945 | Integrated circuit failure prediction An integrated circuit having a frequency generator connected to a constant reference voltage source located on the integrated circuit and a monitor connected to monitor the frequency signal and from the frequency history predicting that an integrated circuit failure... | 07/14/2009 |
| 7548753 | Application for automatic tracking of mobile devices for computer network processor systems A method and system is provided for tracking mobile devices combining packet processing technology with Global Positioning System (GPS) technology. A central network system comprising a packet processing subsystem receives transmitted GPS location data from a mobile... | 06/16/2009 |
| 7529224 | Scheduler, network processor, and methods for weighted best effort scheduling Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a three-... | 05/05/2009 |
| 7526419 | Methods for reconstructing data from simulation models Methods for reconstructing data from simulation models are disclosed. Embodiments may include a method for accessing an alias from an alias file. The method may generally include searching for a net name and, if the net name is not found, searching an alias index fi... | 04/28/2009 |
| 7523265 | Systems and arrangements for promoting a line to exclusive in a fill buffer of a cache Systems and arrangements promoting a line from shared to exclusive in cache are contemplated. Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer ... | 04/21/2009 |
| 7519793 | Facilitating inter-DSP data communications A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core couple... | 04/14/2009 |
| 7512839 | Methods, systems, and media for generating a regression suite database Methods, systems and media for generating an improved regression suite by applying harvesting models and/or regression algorithms to tests utilized in verification of a system are disclosed. In one embodiment, a regression manager responsive to user input may be cou... | 03/31/2009 |
| 7512177 | Method and apparatus for generating random jitter Apparatuses and methods comprise a phase shifter, an adjustable capacitance configured to adjust a phase shift of said phase shifter, an arbitrary waveform generator configured to adjust the adjustable capacitance, and a pulse pattern generator coupled to the phase ... | 03/31/2009 |
| 7506225 | Scanned memory testing of multi-port memory arrays A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The ... | 03/17/2009 |
| 7506081 | System and method of maintaining high bandwidth requirement of a data pipe from low bandwidth memories A Network Processor includes a Fat Pipe Port and a memory sub-system that provides sufficient data to satisfy the Bandwidth requirements of the Fat Pipe Port. The memory sub-system includes a plurality of DDR DRAMs controlled so that data is extracted from one DDR D... | 03/17/2009 |
| 7499470 | Sequence-preserving deep-packet processing in a multiprocessor system Packets or frames of data may be compressed, encrypted/decrypted, filtered, classified, searched or subjected to other deep-packet processing operations before being distributed through the internet. The microprocessor system and method of the present invention prov... | 03/03/2009 |
| 7492013 | Systems and arrangements to interconnect components of a semiconductor device Systems and arrangements to interconnect cells and structures within cells of an integrated circuit to enhance cell density. Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolera... | 02/17/2009 |
| 7490184 | Systems and methods for data intervention for out-of-order castouts Systems and methods for data intervention for out-of-order castouts are disclosed. Embodiments provide for transmitting snoopable requests received from one or more requesting devices to one or more snoopable devices, which may include requesting devices. Each snoop... | 02/10/2009 |
| 7489247 | Wireless system provided in a vehicle to detect presence of child in a baby car seat A wireless system that detects the presence of a child in a safety seat located in the passenger cabin of a vehicle includes a controller responsive to signals generated by sensors monitoring predefined functions of the vehicle, RFID tag device attached to the safet... | 02/10/2009 |
| 7490101 | Method and structure for deleting leaves in tree table structures A technique is provided to delete a leaf from a Patricia tree having a direct table and a plurality of PSCB's which decode portions of the pattern of a leaf in the tree without shutting down the functioning of the tree. A leaf having a pattern is identified as a lea... | 02/10/2009 |
| 7486114 | Signal detector with calibration circuit arrangement A signal detector and method to detect the presence or absence of an incoming differential signal. The method nullifies the DC off-set of the signal detector so that it can detect a signal within a very narrow window. The common mode levels of the signal and referen... | 02/03/2009 |
| 7487542 | Intrusion detection using a network processor and a parallel pattern detection engine An intrusion detection system (IDS) comprises a network processor (NP) coupled to a memory unit for storing programs and data. The NP is also coupled to one or more parallel pattern detection engines (PPDE) which provide high speed parallel detection of patterns in ... | 02/03/2009 |
| 7486683 | Algorithm and system for selecting acknowledgments from an array of collapsed VOQ's A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism. According to the method, an efficient set of virtual output queues (at most one virtual output queue per ingress adap... | 02/03/2009 |
| 7483429 | Method and system for flexible network processor scheduler and data flow A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive t... | 01/27/2009 |
| 7484052 | Distributed address arbitration scheme for symmetrical multiprocessor system The present invention utilizes the good qualities of a single address concentrator (AC), without any extra chips or wires, and distributes the AC function among the various chips, making use of the fact that each chip in the system has a copy of the AC function ther... | 01/27/2009 |
| 7479807 | Leakage dependent online process variation tolerant technique for internal static storage node A device is disclosed for providing compensation current continuously to compensate for leakage current at the node of an electrical circuit, such as a chip. The device includes a dummy storage cell, a single staged current mirror circuit and a non reconfigurable ke... | 01/20/2009 |
| 7478426 | Multi-field classification dynamic rule updates The present invention relates to a method and computer system device for applying a plurality of rules to data packets within a network computer system. A filter rule decision tree is updated by adding or deleting a rule. If deleting a filter rule then the decision ... | 01/13/2009 |
