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| Number | Title | Issue Date |
| 4417946 | Method of making mask for structuring surface areas A mask for structuring surface areas and a method for manufacture thereof. The mask includes at least one metal layer with throughgoing apertures which define the mask pattern and a semiconductor substrate for carrying the metal layer. The semiconductor s... | 11/29/1983 |
| 4410622 | Forming interconnections for multilevel interconnection metallurgy systems A method for forming feedthrough connections, or via studs, between levels of metallization which are typically formed atop semiconductor substrates. A conductive pattern is formed which includes the first level metallurgy, an etch barrier and the feedthr... | 10/18/1983 |
| 4402185 | Thermoelectric (peltier effect) hot/cold socket for packaged I.C. microprobing Disclosed is a two-stage thermoelectric heat pumping apparatus for heating/cooling an I.C. chip. The first stage is a primary thermoelectric module sandwiched between a base made of a high thermal conductivity material and functioning as a heat source/sin... | 09/06/1983 |
| 4391650 | Method for fabricating improved complementary metal oxide semiconductor devices Disclosed is a process for a CMOS integrated circuit having polysilicon conductors of a single conductivity, single impurity type. After forming the conductors they are covered by an oxidation and diffusion mask consisting of a dual layer of silicon dioxi... | 07/05/1983 |
| 4372033 | Method of making coplanar MOS IC structures A method of forming planar silicon structures having recessed dielectric isolation oxide regions in which the bird's beak and bird's head associated with the silicon dioxide-silicon nitride dual mask are eliminated. After forming the pad oxide-nitride dua... | 02/08/1983 |
| 4353083 | Low voltage nonvolatile memory device A low voltage write, avalanche breakdown, nonvolatile MNOSFET memory device. The device is preferably an n-channel enhancement mode, split-gate or trigate structure having a first, relatively highly doped p+ channel region and a second, underlying p-regio... | 10/05/1982 |
| 4345366 | Self-aligned all-n+ polysilicon CMOS process Disclosed is a process for forming self-aligned all n+ -doped polysilicon gates and interconnections in CMOS integrated circuits. Polysilicon is formed into the n-FET gate, a barrier for the p-FET region and the interconnect pattern. Then, arse... | 08/24/1982 |
| 4283660 | Multiline charge transfer panel input and hold system A system for loading a DC multiline plasma charge transfer device and for holding charges applied thereto. Each line of the device includes input and transfer electrodes positioned on opposing walls which define a channel confining an ionizable medium. Th... | 08/11/1981 |
