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| Number | Title | Issue Date |
| 8183639 | Dual port static random access memory cell layout A dual port static random access memory cell has pull-down transistors, pull-up transistors, and pass transistors. A first active region has a first pull-down transistor coupled to a true data node, a second pull-down transistor coupled to a complementary data node;... | 05/22/2012 |
| 8178950 | Multilayered through a via A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium nitride is formed over the adhesion layer, and a tungsten layer is depo... | 05/15/2012 |
| 8178406 | Split gate device and method for forming A method of making a semiconductor device on a semiconductor layer includes forming a select gate, a recess, a charge storage layer, and a control gate. The select gate is formed have a first sidewall over the semiconductor layer. The recess is formed in the semicon... | 05/15/2012 |
| 8178401 | Method for fabricating dual-metal gate device A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited ... | 05/15/2012 |
| 8173505 | Method of making a split gate memory cell A method includes forming a first layer of gate material over a semiconductor substrate; forming a hard mask layer over the first layer; forming an opening; forming a charge storage layer over the hard mask layer and within the opening; forming a second layer of gat... | 05/08/2012 |
| 8169257 | System and method for communicating between multiple voltage tiers A system includes first, second, and third circuits and first and second capacitors. The first capacitor has a first power supply terminal coupled to positive power supply terminal, a second power supply terminal, and an input/output. The second capacitor has a firs... | 05/01/2012 |
| 8158492 | MEMS microphone with cavity and method therefor A device comprises a substrate, a micro electro-mechanical systems (MEMS) structure, and a dielectric film. The substrate has a first side and a second side, the second side opposite the first side. The MEMS structure is formed on the first side of the substrate. Th... | 04/17/2012 |
| 8156805 | MEMS inertial sensor with frequency control and method An inertial sensor has a transducer with a sense resonator. The sense resonator is oscillated. A signal responsive to the oscillation is provided. A first baseband signal and a second baseband signal are provided responsive to the signal responsive to the oscillatio... | 04/17/2012 |
| 8156411 | Error correction of an encoded message An encoded message is stored in a first memory. The encoded message is retrieved from the first memory as a retrieved encoded message that may contain an error. Syndromes are generated from the retrieved encoded message. The syndromes are used to determine if the re... | 04/10/2012 |
| 8156357 | Voltage-based memory size scaling in a data processing system A memory has bits that fail as power supply voltage is reduced to reduce power and/or increase endurance. The bits become properly functional when the power supply voltage is increased back to its original value. With the reduced voltage, portions of the memory that... | 04/10/2012 |
| 8143929 | Flip-flop having shared feedback and method of operation A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, the second node is coupled to a t... | 03/27/2012 |
| 8143126 | Method for forming a vertical MOS transistor A method is used to form a vertical MOS transistor. The method utilizes a semiconductor layer. An opening is etched in the semiconductor layer. A gate dielectric is formed in the opening that has a vertical portion that extends to a top surface of the first semicond... | 03/27/2012 |
| 8143074 | Semiconductor processing system and method of processing a semiconductor wafer A method of processing semiconductor wafers includes applying reactive gas through a plurality of inlets to the semiconductor wafers. The method further includes removing exhaust gas resulting from the step of applying reactive gas. The removing of the exhaust gas i... | 03/27/2012 |
| 8120975 | Memory having negative voltage write assist circuit and method therefor A method of writing data to a selected column of a memory includes selecting a first column. The data writing is initiated by applying a logic high to a first bit line of the first column and a first potential to a second bit line of the first column that is lower t... | 02/21/2012 |
| 8120412 | Voltage boosting system with slew rate control and method thereof A system includes a voltage controlled oscillator, a charge pump, and a current regulator circuit. The voltage controlled oscillator has a control input and a clock output that provides a clock signal at a clock frequency that is variable. The charge pump is coupled... | 02/21/2012 |
| 8119431 | Method of forming a micro-electromechanical system (MEMS) having a gap stop A method of forming a micro-electromechanical system (MEMS) includes providing a cap substrate, providing a support substrate, depositing a conductive material over the support substrate, patterning the conductive material to form a gap stop and a contact, wherein t... | 02/21/2012 |
| 8119334 | Method of making a semiconductor device using negative photoresist Negative photoresist over an insulating layer is exposed to radiation according to a pattern for an opening in the insulating layer for filling conductive material. A post of the negative photoresist is left over the location where the opening in the insulating laye... | 02/21/2012 |
| 8099580 | Translation look-aside buffer with a tag memory and method therefor A translation look-aside buffer (TLB) has a TAG memory for determining if a desired translated address is stored in the TLB. A TAG portion is compared to contents of the TAG memory without requiring a read of the TAG memory because the TAG memory has a storage porti... | 01/17/2012 |
| 8097873 | Phase change memory structures A phase change memory cell has a first electrode, a plurality of pillars, and a second electrode. The plurality of pillars are electrically coupled with the first electrode. Each of the pillars comprises a phase change material portion and a heater material portion.... | 01/17/2012 |
| 8093084 | Semiconductor device with photonics A method for forming a semiconductor structure having a transistor region and an optical device region includes forming a transistor in and on a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulatin... | 01/10/2012 |
| 8090913 | Coherency groups of serially coupled processing cores propagating coherency information containing write packet to memory A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a... | 01/03/2012 |
| 8080439 | Method of making a vertical phase change memory (PCM) and a PCM device A method of making a phase change random access memory (PCM) device comprises forming a PCM stack that includes a heater layer, phase change material layer, and a top electrode layer. A top protection layer is formed overlying the PCM stack. The top protection layer... | 12/20/2011 |
| 8077839 | Handheld device for dialing of phone numbers extracted from a voicemail A method for processing a telephone number embedded in a voicemail received by a user of the handheld device comprising a processor and a memory is provided. The method includes playing back the voicemail. The method further includes in response to receiving a first... | 12/13/2011 |
| 8059482 | Memory using multiple supply voltages A memory has a method of operating that includes performing operations of a first type and a second type. A first voltage is coupled to a power supply node of a first memory cell of a memory array during a first operation of the first type. The first voltage is deco... | 11/15/2011 |
| 8059380 | Package level ESD protection and method therefor A semiconductor package includes an electrostatic discharge rail capable of being coupled to a first conductive contact and a second conductive contact, a first portion of a voltage triggerable material between the electrostatic discharge rail and the first conducti... | 11/15/2011 |
| 8058143 | Substrate bonding with metal germanium silicon material A method that in one embodiment is useful in bonding a first substrate to a second substrate includes forming a layer including metal over the first substrate. The layer including metal in one embodiment surrounds a semiconductor device, which can be a micro electro... | 11/15/2011 |
| 8049549 | Delta phi generator with start-up circuit A circuit comprises a delta phi generator, a startup circuit, and a level detector. The delta phi generator has a desirable operating state for developing a delta phi voltage at an output node in response to an input voltage, and an undesirable operating state. The ... | 11/01/2011 |
| 8043888 | Phase change memory cell with heater and method therefor A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silic... | 10/25/2011 |
| 8041132 | System and method for load balancing a video signal in a multi-core processor Sequential video data frames are encoded using cores including a first core and a second core. A first beginning frame is divided into slices. The first core is assigned to process a first slice. The second core is assigned to process a second slice. The first begin... | 10/18/2011 |
| 8039389 | Semiconductor device having an organic anti-reflective coating (ARC) and method therefor In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperatu... | 10/18/2011 |
| 8039339 | Separate layer formation in a semiconductor device A semiconductor device is formed. A first gate dielectric layer is formed over the semiconductor layer. A first conductive layer is formed over the first gate dielectric. A first separation layer is formed over the first conductive layer. A trench is formed in the s... | 10/18/2011 |
| 8039312 | Method for forming a capped micro-electro-mechanical system (MEMS) device A capped micro-electro-mechanical systems (MEMS) device is formed using a device wafer and a cap wafer. The MEMS device is located on a frontside of the device wafer. A frontside of a cap wafer is attached to the frontside of the device wafer. A first stressor layer... | 10/18/2011 |
| 8032030 | Multiple core system An integrated circuit has a group of cores that communicate with a packet switch using carrierless ultra wideband (UWB) radio frequency (RF) signaling. The packet switch communicates outside the integrated circuit using optical signaling. The carrierless UWB provide... | 10/04/2011 |
| 8026760 | Gain enhanced switched capacitor circuit and method of operation A switched capacitor circuit utilizes a pair of serially connected differential amplifiers that have plus inputs, minus inputs, plus outputs, and minus outputs. Feedback to the plus/minus inputs is in a first configuration relative to the output of the pair of diffe... | 09/27/2011 |
| 8026700 | DC to DC converter having switch control and method of operation In a D.C. to D.C. converter, an input voltage is received via an inductor at an input terminal and stored onto a capacitor of an integrator. A first switch is coupled between the input terminal and a reference terminal such as ground and thereby fluxes the inductor.... | 09/27/2011 |
| 8014457 | Method of providing a data signal for channel estimation and circuit thereof A received signal having pilots is converted to a first signal in the frequency domain having the pilots. The pilots are extracted from the first signal to obtain extracted pilots to form a second signal. The second signal is used to provide a first estimate of a ch... | 09/06/2011 |
| 8010854 | Method and circuit for brownout detection in a memory system Detecting brown-out in a system having a non-volatile memory (NVM) includes loading data in the NVM, wherein a next step in loading is performed on a location in the NVM that is logically sequential to an immediately preceding loading. A pair of adjacent locations i... | 08/30/2011 |
| 8009489 | Memory with read cycle write back A memory has a first bit line, a second bit line, and a word line. A memory cell is coupled to the word line and the first and second bit lines. A sense amplifier has a first input, a second input, a first output, and a second output. A pair of coupling transistors ... | 08/30/2011 |
| 8008964 | Variable input voltage charge pump A device for providing a constant output voltage based on a variable input voltage is provided. The device may include: (1) a charge-pump comprising a plurality of cells, wherein each of the plurality of cells can be configured as an input cell, a stepping cell, or ... | 08/30/2011 |
| 8004907 | SRAM with read and write assist A memory includes an SRAM bitcell including a pair of cross-coupled inverters, wherein a first inverter of the pair includes a first device having a body and a second inverter of the pair includes a second device having a body. A first selection circuit has a first ... | 08/23/2011 |
