Famous Patents
Pong, the Atari creation that launched the computer game craze, came with these instructions: "Avoid missing ball for high score."
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 6435737 | Data pipeline system and data encoding method A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and... | 08/20/2002 |
| 6217234 | Apparatus and method for processing data with an arithmetic unit An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both con... | 04/17/2001 |
| 6035126 | Data pipeline system and data encoding method A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and... | 03/07/2000 |
| 5984512 | Method for storing video information An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both con... | 11/16/1999 |
| 5910960 | Signal processing apparatus and method A CMOS Reed-Solomon decoding circuit calculates syndromes, executes a Berlekamp algorithm, performs a Chien Search, and corrects a delayed version of the received data according to a calculated magnitude of error. The circuit is optimized in terms of chip... | 06/08/1999 |
| 5878273 | System for microprogrammable state machine in video parser disabling portion of processing stages responsive to sequence-- end token generating by token generator responsive to received data An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both con... | 03/02/1999 |
| 5861894 | Buffer manager This invention provides a method to control the buffering of encoded video data organized as frames or fields. This method involves determining the picture number of each incoming decoded frame, determining the expected presentation number at any time and... | 01/19/1999 |
| 5842033 | Padding apparatus for passing an arbitrary number of bits through a buffer in a pipeline system A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and... | 11/24/1998 |
| 5835792 | Token-based adaptive video processing arrangement An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both con... | 11/10/1998 |
| 5835740 | Data pipeline system and data encoding method A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and... | 11/10/1998 |
| 5829007 | Technique for implementing a swing buffer in a memory array A RAM implementation of asynchronous swing buffering is provided in which two buffers are operated asynchronously; one is written while the other is read. Accordingly, this allows for a data stream having a fast rate of through-put to be resynchronized to... | 10/27/1998 |
| 5828907 | Token-based adaptive video processing arrangement An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arrangedas a pipeline processing machine. Control tokens and DATA Tokens pass ovef the single two-wire interface for carrying both cont... | 10/27/1998 |
| 5821885 | Video decompression An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both con... | 10/13/1998 |
| 5818855 | Galois field multiplier for Reed-Solomon decoder A Reed-Solomon decoder includes an optimized Galois Field multiplication circuit. The circuit has a plurality of multipliers, connected in a linear chain, wherein a first multiplicand of the first multiplier is the magnitude A, and the second multiplicand... | 10/06/1998 |
| 5809270 | Inverse quantizer A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and... | 09/15/1998 |
| 5805914 | Data pipeline system and data encoding method A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and... | 09/08/1998 |
| 5801973 | Video decompression An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both con... | 09/01/1998 |
| 5798719 | Parallel Huffman decoder A Huffman Decoder is provided for decoding a data stream of fixed length and variable length codes and is adapted for video decompression applications. In the case of variable length codes, a table index calculation is performed using a ROM whose addresse... | 08/25/1998 |
| 5792479 | Technique for acceleration of apoptotic cell death A first embodiment of a cell culture system has a cell death accelerator comprising one or more cell death inducing substances, including serum albumin, hemoglobin, glycine and glutamic acid. In a second embodiment a cell death inhibitor comprises one or ... | 08/11/1998 |
| 5793818 | Signal processing system A CMOS integrated signal processing system for a sampling receiver includes a timing recovery circuit, wherein an on-chip numerically controlled oscillator is operative at periods T that are initially equal to the nominal baud rate of the signals controls... | 08/11/1998 |
| 5784631 | Huffman decoder A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and... | 07/21/1998 |
| 5768561 | Tokens-based adaptive video processing arrangement A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and... | 06/16/1998 |
| 5768629 | Token-based adaptive video processing arrangement An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both con... | 06/16/1998 |
| 5761210 | Signal processing apparatus and method An integrated CMOS circuit is disclosed for deinterleaving transmitted data packets. The circuit operates with a RAM buffer that is no larger than a block of interleaved data. An optimized addressing scheme is provided that minimizes on-chip hardware. The... | 06/02/1998 |
| 5761741 | Technique for addressing a partial word and concurrently providing a substitution field A method and apparatus for addressing memory is disclosed. In one embodiment, a procedure for providing a word with fixed width, having a fixed number of bits to be used for addressing variable width data, and having a width defining field and address fie... | 06/02/1998 |
| 5740460 | Arrangement for processing packetized data An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both con... | 04/14/1998 |
| 5724396 | Signal processing system A CMOS integrated signal processing system for a sampling receiver includes a timing recovery circuit, wherein an on-chip numerically controlled oscillator is operative at periods T that are initially equal to the nominal baud rate of the signals controls... | 03/03/1998 |
| 5724537 | Interface for connecting a bus to a random access memory using a two wire link The invention provides a RAM interface for connecting a bus to RAM wherein a separate address generator generates the addresses the RAM interface needs to address the RAM. The interface utilizes a plurality of swing buffers, and has a control module for c... | 03/03/1998 |
| 5717715 | Signal processing apparatus and method An integrated digital communication system utilizing multilevel vestigial sideband transmission is provided. The communication system receives a multi-level pulse-amplitude modulated digital signal from a limited bandwidth channel. The system includes pro... | 02/10/1998 |
| 5703793 | Video decompression An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both con... | 12/30/1997 |
| 5699544 | Method and apparatus for using a fixed width word for addressing variable width data A method for addressing memory uses a word with a fixed width, having a fixed number of bits, and having a width defining field and address field. The procedure is adapted to addressing variable width data. In one embodiment memory can be addressed using ... | 12/16/1997 |
| 5692020 | Signal processing apparatus and method An integrated digital communication system utilizing multilevel vestigial sideband transmission is provided. The communication system receives a multi-level pulse-amplitude modulated digital signal from a limited bandwidth channel. The system includes pro... | 11/25/1997 |
| 5689485 | Tracking control apparatus and method An apparatus is disclosed for control of a beam of radiant energy, wherein a detector of the beam has first and second outputs responsive to a position of the beam. A circuit is coupled to the outputs of the detector for producing an error signal represen... | 11/18/1997 |
| 5689313 | Buffer management in an image formatter This invention provides a method to control the buffering of encoded video data organized as frames or fields. This method involves determining the picture number of each incoming decoded frame, determining the expected presentation number at any time and... | 11/18/1997 |
| 5677648 | Noise compensated phase locked loop circuit An improved phase locked loop utilizing control logic generated by a phase detector to eliminate sensitivity to uncorrelated noise when the loop is in lock.... | 10/14/1997 |
| 5668831 | Signal processing apparatus and method An integrated digital communication system utilizing multilevel vestigial sideband transmission is provided. The communication system receives a multi-level pulse-amplitude modulated digital signal from a limited bandwidth channel. The system includes pro... | 09/16/1997 |
| 5635864 | Comparator circuit A high speed analog-to-digital converter employs a comparator having first and second units cross coupled in a positive feedback loop. The units are alternately connected to an input voltage and a reference voltage, after which positive feedback is introd... | 06/03/1997 |
| 5625571 | Prediction filter An apparatus is disclosed for processing video information using a first and a second prediction filter circuit which are substantially identical, and a control signal to process video information encoded in multiple standards. A filter circuit, such as m... | 04/29/1997 |
| 5617458 | Clock divider The invention discloses a method and an apparatus for implementing an L phase clock in conjuction with L counters, where L is an integer, to count at a frequency scalable by L.... | 04/01/1997 |
| 5603012 | Start code detector A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and... | 02/11/1997 |
