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| Number | Title | Issue Date |
| 7302160 | Audio/video recorder with automatic commercial advancement prevention A method for automatically advancing an audio/video signal past undesirable material comprising the steps of (A) detecting possible triggering events during encoding of said audio/video signal, (B) generating one or more scores of various levels in response to said ... | 11/27/2007 |
| 7231587 | Embedded picture PSNR/CRC data in compressed video bitstream A method for processing an input signal is disclosed. The method generally includes the steps of (A) extracting a compressed signal and a first checksum from the input signal, (B) generating a decompressed signal by decompressing the compressed signal, (C) calculati... | 06/12/2007 |
| 7215584 | Method and/or apparatus for training DQS strobe gating A method for calibrating read data strobe gating including the steps of: (A) performing a coarse timing adjustment configured to determine a coarse delay setting that produces invalid data, (B) performing a medium timing adjustment configured to adjust a medium dela... | 05/08/2007 |
| 7191424 | Special tie-high/low cells for single metal layer route changes A method for implementing a circuit design is disclosed. The method generally includes the steps of identifying, replacing and routing. The first step may identify a first cell of the circuit design having (i) a function and (ii) an input pin connectable to one of a... | 03/13/2007 |
| 7117420 | Construction of an optimized SEC-DED code and logic for soft errors in semiconductor memories An apparatus for memory error control coding comprising a first circuit and a second circuit. The first circuit may be configured to generate a multi-bit digital syndrome signal in response to a read data signal and a read parity signal. The second circuit may be co... | 10/03/2006 |
| 7111319 | Set top box access hub system An apparatus comprising an audio/video decoder and a storage device. The audio/video decoder may be configured to receive (i) one or more uncompressed audio signals and (ii) one or more compressed audio/video signals. The uncompressed audio signals may be tagged to ... | 09/19/2006 |
| 7085177 | Maximum swing thin oxide levelshifter An apparatus comprising a first transistor pair, second transistor pair, a third transistor pair and a fourth transistor pair. The first transistor pair may be (i) implemented as thin oxide devices and (ii) configured to receive a differential input signal. The seco... | 08/01/2006 |
| 7076439 | Method and apparatus for managing multiple projects The present invention is a computer-based system for managing projects. It allows the user to input data concerning a project and associate individuals with the project. The system then determines a deadline for completing a task associated with the project and send... | 07/11/2006 |
| 7062736 | Timing constraint generator A method for generating a plurality of timing constraints for a circuit design is disclosed. The method generally includes the steps of (A) identifying a plurality of clock signals by analyzing the circuit design, (B) determining a plurality of relationships among t... | 06/13/2006 |
| 7047335 | Method for receiving user defined frame information structure (FIS) types in a serial-ATA (SATA) system An apparatus comprising one or more user programmable registers and a circuit configured to compare a predetermined portion of one or more information packets with contents of said one or more user programmable registers. ... | 05/16/2006 |
| 7039064 | Programmable transmission and reception of out of band signals for serial ATA An apparatus generally comprising a plurality of writeable registers, a control circuit, and a transmitter circuit. The writeable registers may be configured to store (i) a first burst value and (ii) a first gap value. The control circuit may be configured to genera... | 05/02/2006 |
| 7039298 | Extraction of audio/visual segment from digital versatile disk content A segment of audio/visual (A/V) content is extracted from the overall DVD content of a DVD program or disk. A DVD player with A/V segment extraction functionality receives commands from a user that identify start and stop points in the DVD content for the desired A/... | 05/02/2006 |
| 7039756 | Method for use of ternary CAM to implement software programmable cache policies A method of operating a circuit is disclosed. The method generally comprises the steps of (A) generating a particular policy of a plurality of policies by a lookup operation on a first transaction request received by the circuit, (B) generating a second transaction ... | 05/02/2006 |
| 7032104 | Configurable hardware register stack for CPU architectures A circuit comprising a register stack and a control circuit. The register stack may be configured as (i) a plurality of segments addressable through a segment address signal and (ii) a plurality of registers within each of the plurality of segments. The plurality of... | 04/18/2006 |
| 7027526 | Time multiplexing bus for DTV common interface A device for use in a digital video receiver. The device generally comprising a demodulator circuit, a decoder circuit, a plurality of bi-directional buffers, and a circuit. The demodulator circuit may be configured to generate (i) a first clock signal compliant wit... | 04/11/2006 |
| 7028276 | First time silicon and proto test cell notification A method for notification of a first new cell is disclosed. The method generally includes the steps of (A) generating a first report for a circuit design comprising a plurality of first cells including the first new cell by executing a rule check on the circuit desi... | 04/11/2006 |
| 7023801 | Speculative packet selection for transmission of isochronous data A refetch logic propagates data from a first source to a link controller by default. The link controller prefetches data from the refetch logic to generate a first packet prior to receiving control of the transmission medium on which the data is to be transmitted. T... | 04/04/2006 |
| 7020892 | Time-shifted video signal processing A time-shifted video method has a real-time mode during which real-time video frames are delivered for display. In a time-shifted mode, time-shifted video frames are delivered for display. The time-shifted video frames are delayed relative to the real-time video fra... | 03/28/2006 |
| 7016794 | Floor plan development electromigration and voltage drop analysis tool A method for analyzing electromigration and voltage drop effects in wire segments forming a power-bus grid of an integrated circuit. A floor plan design is created by mapping wire segments to various metal layers in the IC core. Digital, analog, and memory power zon... | 03/21/2006 |
| 7017126 | Metacores: design and optimization techniques A method for developing a circuit is disclosed. The method generally comprises the steps of (A) generating a solution space having a dimension for each of a plurality of parameters for the circuit, (B) evaluating a plurality of instances of the circuit in the soluti... | 03/21/2006 |
| 7010046 | Method and/or architecture for implementing MPEG frame display using four frame stores An apparatus comprising a decode frame store, a B frame store, a first anchor frame store, and a second anchor frame store. The decode frame store may be configured to decode one or more free frames and generate one or more B video images and one or more anchor vide... | 03/07/2006 |
| 7007201 | Shared embedded trace macrocell An apparatus generally comprising a plurality of processors, a trace circuit, and a connector circuit. The trace circuit may be configured to present information at a port for debugging software in a selected processor of the processors. The connector circuit may be... | 02/28/2006 |
| 7007108 | System method for use of hardware semaphores for resource release notification wherein messages comprises read-modify-write operation and address A method for resource notification is disclosed. The method generally comprises the steps of (A) buffering a plurality of messages received from a plurality of busses, (B) arbitrating among the messages, (C) writing the messages in response to the arbitration, and (... | 02/28/2006 |
| 7000163 | Optimized buffering for JTAG boundary scan nets An apparatus comprising one or more groups of boundary scan cells, one or more group buffers, one or more repeater buffers and a controller. The group buffers may be coupled to each of the groups of boundary scan cells. The repeater buffers may be coupled in series ... | 02/14/2006 |
| 6940909 | Video decoding during I-frame decode at resolution change A method of buffering a video signal is disclosed. The method generally includes the steps of (A) storing a plurality of pictures decoded from the video signal having a first resolution in a memory space divided into a plurality of first buffers each having a first ... | 09/06/2005 |
| 6925181 | Method of protecting high definition video signal A system controls reproduction of a video transmission between a transmitter and a receiver. The system includes an encryptor with an offset generator adapted to receive the encrypted frame key and to generate a sequence of pseudo-random values for the color compone... | 08/02/2005 |
| 6922823 | Method for creating derivative integrated circuit layouts for related products A method for creating a derivative semiconductor design layout is disclosed. The method generally comprises the steps of (A) receiving a plurality of changes from a user for a first layout of a semiconductor design having a plurality of first layers, (B) storing the... | 07/26/2005 |
| 6920510 | Time sharing a single port memory among a plurality of ports An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to transfer data between a plurality of first ports and a second port via a single port memory in response to one or more control signals. The second circuit may be con... | 07/19/2005 |
| 6901022 | Proportional to temperature voltage generator A biasing circuit comprising a first circuit and a second circuit. The first circuit may be configured to generate a first bias signal and a second bias signal. The second bias signal may be defined by a threshold voltage and a first resistance. The second circuit m... | 05/31/2005 |
| 6831654 | Data processing system A data processing system comprising a block move engine, a memory, a register and a reader. The block move engine may be configured to process data. The memory may be configured to store data in the form of a linked list comprising a plurality of items of control da... | 12/14/2004 |
| 6819539 | Method for circuit recovery from overstress conditions A method for circuit recovery from overstress conditions, comprising the steps of (A) detecting an event and (B) resetting a device when the event is a first predetermined type and providing recovery when the event is a second predetermined type. ... | 11/16/2004 |
| 6816955 | Logic for providing arbitration for synchronous dual-port memory An apparatus for providing arbitration for a dual-port memory. The apparatus may be configured to prevent a write cycle extension during contention between simultaneous read and write operations. ... | 11/09/2004 |
| 6816979 | Configurable fast clock detection logic with programmable resolution An apparatus comprising a first logic circuit and a second logic circuit. The first logic circuit may comprise one or more counters and may be configured to synchronize a plurality of input clock signals. The second logic circuit may be configured to detect and pres... | 11/09/2004 |
| 6813672 | EMC enhancement for differential devices An apparatus configured to communicate through a differential bus to a device. The apparatus may be configured to disconnect and reconnect the device in response to an abnormal reset event to provide enhanced electromagnetic compliance (EMC). ... | 11/02/2004 |
| 6806778 | Darlington cascode An apparatus comprising a Darlington transistor pair and a common-base transistor. The Darlington transistor pair may be configured to generate an output signal at an output node in response to an input signal received through an input node. The common-base transist... | 10/19/2004 |
| 6799227 | Dynamic configuration of a time division multiplexing port and associated direct memory access controller An apparatus comprising a transmit data path, a receive data path, a first circuit and a second circuit. The first circuit may be configured to transfer data between a first interface and the transmit and receive data paths. The second circuit may be configured (i) ... | 09/28/2004 |
| 6791366 | Circuit for implementing product term inputs An apparatus comprising a polarity switch. The polarity switch may comprise a number of transmission gates. An output of the polarity switch may selectably present either (i) a signal that varies in response to a control signal or (ii) a predetermined logic level th... | 09/14/2004 |
| 6788098 | Test structures for simultaneous switching output (SSO) analysis An apparatus comprising a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate a plurality of intermediate signals from a data signal. Each of the intermediate signals may be switchable between (i) a commo... | 09/07/2004 |
| 6782467 | Method and apparatus for fast limited core area access and cross-port word size multiplication in synchronous multiport memories An apparatus comprising a control circuit and a generation circuit. The control circuit may be configured to generate a mask signal, a unique counter control signal, and an incremented state signal in response to an address signal and a counter control signal. The g... | 08/24/2004 |
| 6779061 | Method and apparatus implementing a FIFO with discrete blocks An apparatus comprising one or more storage elements. The one or more storage elements may be configured to switch an input/output between a first domain and a second domain in response to one or more control signals. ... | 08/17/2004 |
