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| Number | Title | Issue Date |
| 8185854 | Method and apparatus for performing parallel slack computation within a shared netlist region A method for designing a system on a target device is disclosed. Domains and sub-domains in the system are identified. A sub-domain is divided into a plurality of chunks. Slacks for the chunks are computed in parallel. Other embodiments are described and claimed. | 05/22/2012 |
| 8185714 | Method and apparatus for strobe-based source-synchronous capture using a first-in-first-out unit A source-synchronous capture unit includes a data register unit to register data synchronized to a strobe or non-free running clock. The source synchronous capture unit also includes an asynchronous first-in-first-out (FIFO) unit to store the data from the data regi... | 05/22/2012 |
| 8181025 | Method and apparatus for registering agents onto a virtual machine monitor A method for managing an agent includes verifying an integrity of the agent in response to a registration request. Memory protection is provided for the agent during integrity verification. An indication is generated when registration of the agent has been completed... | 05/15/2012 |
| 8176450 | Method and apparatus for parameterizing hardware description language code in a system level design environment A method for managing an electronic design automation tool includes importing a component. A graphical user interface is generated to allow a user to enter values for parameters of the component. Other embodiments are disclosed. ... | 05/08/2012 |
| 8165033 | Method and apparatus for performing generalized processor sharing scheduling A scheduler includes a sorting unit that has n comparators to identify a smallest virtual finish time (VFT) value from 2n VFT entries. Each of the VFT entries may include a valid bit to indicate its validity. ... | 04/24/2012 |
| 8156463 | Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool for routing A method for designing a system includes determining minimum and maximum delay budgets for connections. Routing resources are selected for connections in response to the minimum and maximum delay budgets. ... | 04/10/2012 |
| 8156452 | Method and apparatus for importing hardware description language into a system level design environment A method for importing a design in hardware description language (HDL) into a system level design tool includes setting a sampling time. The simulation model template is generated with the sampling time according to a selected simulation model type. ... | 04/10/2012 |
| 8141018 | Method and apparatus for using slack potential data to design a system on a field programmable gate array A method for designing a system to be implemented on a target device includes computing slack potential of paths between components on the target device after timing analysis. A graphical representation of the slack potential and slack for the paths is generated. Th... | 03/20/2012 |
| 8120112 | Method and apparatus for improving triggering uniformity of snapback electrostatic discharge protection devices An electrostatic discharge (ESD) protection circuit includes a first array of transistors, having source and drain doped with a first type of material, arranged in parallel in a first block, and a second array of transistors, having source and drain doped with the f... | 02/21/2012 |
| 8095906 | Method and apparatus for performing parallel routing using a multi-threaded routing procedure A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system ... | 01/10/2012 |
| 8065441 | Method and apparatus for supporting universal serial bus devices in a virtualized environment A method for performing virtualization, includes managing data between a virtual machine and a bus controller by transmitting an input output (IO) request from the virtual machine to a service virtual machine that owns the bus controller. According to an alternate e... | 11/22/2011 |
| 8046729 | Method and apparatus for composing and decomposing low-skew networks A logic device includes a low-skew network that feeds a subset of elements on the logic device. The low-skew network includes a selector that can select from a plurality of signal sources which includes a first signal source and a second signal source, wherein the s... | 10/25/2011 |
| 8032855 | Method and apparatus for performing incremental placement on a structured application specific integrated circuit A method for placing a system on a structured application specific integrated circuit (ASIC) using an electronic design automation tool is disclosed. A subregion that includes an illegal position in a placement solution is identified. All structured ASIC cells in th... | 10/04/2011 |
| 8024715 | Method and apparatus for detecting transient faults via dynamic binary translation A method for detecting transient fault includes translating binary code to an intermediate language code. An instruction of interest in the intermediate language code is identified. Reliability instructions are inserted in the intermediate language code to validate ... | 09/20/2011 |
| 8015524 | Method and apparatus for performing incremental delay annotation A method for designing a system on a target device includes identifying components and routing connections impacted by incremental design changes made to a system design. New information is computed to annotate delays for the components and routing connections ident... | 09/06/2011 |
| 8015382 | Method and apparatus for strobe-based source-synchronous capture using a first-in-first-out unit A source-synchronous capture unit includes a data register unit to register data synchronized to a strobe or non-free running clock. The source synchronous capture unit also includes an asynchronous first-in-first-out (FIFO) unit to store the data from the data regi... | 09/06/2011 |
| 7996797 | Method and apparatus for performing multiple stage physical synthesis A method for designing a system on a target device includes entering the system. The system is synthesized. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system immediately after more th... | 08/09/2011 |
| 7987222 | Method and apparatus for implementing a multiplier utilizing digital signal processor block memory extension A method for performing multiplication on a field programmable gate array includes generating a product by multiplying a first plurality of bits from a first number and a first plurality of bits from a second number. A stored value designated as a product of a secon... | 07/26/2011 |
| 7983909 | Method and apparatus for encoding audio data A method for processing audio data includes determining a first common scalefactor value for representing quantized audio data in a frame. A second common scalefactor value is determined for representing the quantized audio data in the frame. A line equation common ... | 07/19/2011 |
| 7975263 | Method and apparatus for generating run time profiles for program compilation A method for managing a profile includes generating an initial profile of code using an initial sampling frequency. An information entropy value of the profile is computed. A representative profile of the code is determined from additional profiles using a sampling ... | 07/05/2011 |
| 7958466 | Method and apparatus for calculating a scalar quality metric for quantifying the quality of a design solution A method for generating a scalar quality metric value for a design solution includes reflectings one or more qualities of the design solution with respect to two or more domains in the system. Other embodiments are also disclosed. ... | 06/07/2011 |
| 7913236 | Method and apparatus for performing dynamic optimization for software transactional memory A method for managing a transaction includes determining that an optimistically immutable field in the transaction is written to. Invaliding a method in response to determining that the method in the transaction reads is the optimistically immutable field. Ot... | 03/22/2011 |
| 7913203 | Method and apparatus for designing a system on multiple field programmable gate array device types A method for designing a system to be implemented on a target device includes generating a register transfer language (RTL) representation of the system from a description of the system without pipelined delays. The RTL representation of the system includes pipeline... | 03/22/2011 |
| 7902953 | Method and apparatus for improving inductor performance using multiple strands with transposition A spiral inductor includes a winding that includes a plurality of strands. The spiral inductor also includes a plurality of tracks where a first set of tracks is positioned adjacent to one another on a first of layer and a second set of tracks is positioned adjacent... | 03/08/2011 |
| 7895549 | Method and apparatus for implementing a processor interface block with an electronic design automation tool An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array (FPGA) includes a library that includes a processor interface block selectable by a designer to represent a component in the design that is accessible to ... | 02/22/2011 |
| 7883946 | Angled implantation for deep submicron device optimization A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a ... | 02/08/2011 |
| 7877710 | Method and apparatus for deriving signal activities for power analysis and optimization A method for managing vectorless estimation includes identifying a semantic structure. A signal activity is assigned to an output of the semantic structure. Vectorless estimation is performed on non-semantic structures. ... | 01/25/2011 |
| 7873934 | Method and apparatus for implementing carry chains on field programmable gate array devices A method for designing a system to be implemented on a field programmable gate array (FPGA) includes identifying an adder from an intermediate representation of the system. Components on the target device are designated to support and implement the adder as a partit... | 01/18/2011 |
| 7853911 | Method and apparatus for performing path-level skew optimization and analysis for a logic design A method for designing a system including optimizing path-level skew in the system and analyzing path-level skew in the system. Other embodiments are also disclosed. ... | 12/14/2010 |
| 7823092 | Method and apparatus for implementing a parameterizable filter block with an electronic design automation tool An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array (FPGA) includes a graphical user interface to create a block based schematic. The EDA tool includes a library that includes a parameterizable filter block... | 10/26/2010 |
| 7818705 | Method and apparatus for implementing a field programmable gate array architecture with programmable clock skew A skew generator unit includes a delay chain. The delay chain is coupled to a clock line that transmits a clock signal. The delay chain generates a skewed clock signal having a unit of delay from the clock signal. The skew generator unit also includes a selector. Th... | 10/19/2010 |
| 7809161 | Method and apparatus for three-dimensional tracking of infra-red beacons A method for processing data includes identifying a time signature of an infra-red (IR) beacon. Image data associated with the IR beacon is identified using the time signature. ... | 10/05/2010 |
| 7801937 | Method and apparatus for implementing a look-ahead for low radix Montgomery multiplication A method for performing Montgomery multiplication on n bit numbers includes computing look-ahead partial sum values to generate a Montgomery result after n/2+1 iterations of intermediate result computations. According to one embodiment of the present invention, Mont... | 09/21/2010 |
| 7797699 | Method and apparatus for scheduling virtual machine access to shared resources A method for managing IO requests from a virtual machine to access IO resources on a physical machine includes determining a request priority associated with an IO request. The IO request is placed in an appropriate queue in response to determining the request prior... | 09/14/2010 |
| 7793248 | Method and apparatus for parameterizing hardware description language code in a system level design environment A method for managing an electronic design automation tool includes importing a component. A graphical user interface is generated to allow a user to enter values for parameters of the component. Other embodiments are disclosed. ... | 09/07/2010 |
| 7788614 | Method and apparatus for performing analytic placement techniques on logic devices with restrictive areas A method for designing a system on a target device having restricted areas includes determining locations on the target device for all cells in the system by solving one or more equations. The one or more equations are modified, or supplemented by adding one or more... | 08/31/2010 |
| 7782581 | Method and apparatus for providing electrostatic discharge protection for a polysilicon fuse An electrostatic discharge (ESD) protection circuit for protecting a component on a device includes a grounding element coupled to a protected supply voltage line of the component. A supply pass element is coupled to the protected supply voltage line of the componen... | 08/24/2010 |
| 7774729 | Method and apparatus for reducing dynamic power in a system A method for designing a system on a target device includes inserting sequential elements into combinatorial logic bounded by a source sequential element and a destination sequential element to reduce glitching. The sequential elements are clocked with a clock signa... | 08/10/2010 |
| 7757197 | Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device A method for designing a system on a programmable logic device (PLD) is disclosed. Routing resources are selected for a user specified signal on the PLD in response to user specified routing constraints. Routing resources are selected for a non-user specified signal... | 07/13/2010 |
| 7739466 | Method and apparatus for supporting immutable memory A method for managing a memory in a computer system is disclosed. A mapping of a virtual page to physical page is locked in response to receiving a request to make the page immutable. According to an aspect of an embodiment of the invention, locking the mapping of t... | 06/15/2010 |
