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| Number | Title | Issue Date |
| 8180969 | Cache using pseudo least recently used (PLRU) cache replacement with locking A cache stores information in each of a plurality of cache lines. Addressing circuitry receives memory addresses for comparison with multiple ways of stored addresses to determine a hit condition representing a match of a stored address and a received address. A pse... | 05/15/2012 |
| 8178406 | Split gate device and method for forming A method of making a semiconductor device on a semiconductor layer includes forming a select gate, a recess, a charge storage layer, and a control gate. The select gate is formed have a first sidewall over the semiconductor layer. The recess is formed in the semicon... | 05/15/2012 |
| 8173505 | Method of making a split gate memory cell A method includes forming a first layer of gate material over a semiconductor substrate; forming a hard mask layer over the first layer; forming an opening; forming a charge storage layer over the hard mask layer and within the opening; forming a second layer of gat... | 05/08/2012 |
| 8163615 | Split-gate non-volatile memory cell having improved overlap tolerance and method therefor A method for forming a split-gate non-volatile memory (NVM) cell includes forming a first gate layer over a semiconductor substrate; forming a conductive layer over the first gate layer; patterning the first gate layer and the conductive layer to form a first sidewa... | 04/24/2012 |
| 8156357 | Voltage-based memory size scaling in a data processing system A memory has bits that fail as power supply voltage is reduced to reduce power and/or increase endurance. The bits become properly functional when the power supply voltage is increased back to its original value. With the reduced voltage, portions of the memory that... | 04/10/2012 |
| 8145985 | Error detection schemes for a unified cache in a data processing system In a data processing system processing circuitry executes a plurality of data processing instructions. A unified cache memory stores data and instructions processed by the processing circuitry. The unified cache memory has a plurality of sets, each set having a plur... | 03/27/2012 |
| 8143929 | Flip-flop having shared feedback and method of operation A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, the second node is coupled to a t... | 03/27/2012 |
| 8143126 | Method for forming a vertical MOS transistor A method is used to form a vertical MOS transistor. The method utilizes a semiconductor layer. An opening is etched in the semiconductor layer. A gate dielectric is formed in the opening that has a vertical portion that extends to a top surface of the first semicond... | 03/27/2012 |
| 8131951 | Utilization of a store buffer for error recovery on a store allocation cache miss A processor and cache is coupled to a system memory via a system interconnect. A first buffer circuit coupled to the cache receives one or more data words and stores the one or more data words in each of one or more entries. The one or more data words of a first ent... | 03/06/2012 |
| 8131948 | Snoop request arbitration in a data processing system A snoop look-up operation is performed in a system having a first cache and a first processor. The first processor generates access requests to the first cache for data. Snoop look-up operations are performed in the cache. The snoop look-up operations are based on s... | 03/06/2012 |
| 8131947 | Cache snoop limiting within a multiple master data processing system In a data processing system, access to a cache in response to access requests from first processing circuitry and snoop requests resulting from a transaction performed by second processing circuitry are arbitrated. Accesses to the cache are monitored to determine if... | 03/06/2012 |
| 8099560 | Synchronization mechanism for use with a snoop queue In a data processing system each bus master of a plurality of bus masters communicates information via a system interconnect. A cache is associated with a predetermined bus master of the plurality of bus masters for storing information used by the predetermined bus ... | 01/17/2012 |
| 8095831 | Programmable error actions for a cache in a data processing system A data processing system and method of operation has a processor coupled to a cache. Cache control circuitry is coupled to the cache and performs error detection. A user programmable error action control register stores a control value for selecting a type of error ... | 01/10/2012 |
| 8093084 | Semiconductor device with photonics A method for forming a semiconductor structure having a transistor region and an optical device region includes forming a transistor in and on a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulatin... | 01/10/2012 |
| 8080444 | Method for forming a packaged semiconductor device having a ground plane A method of placing a die includes providing an embedded plane. The embedded plane has a openings, grid lines, and protruding portions. Each of the plurality of openings are surrounding by a subset of the plurality of grid lines. At least one of the protruding porti... | 12/20/2011 |
| 8060730 | Selective MISR data accumulation during exception processing A plurality of test points are located at predetermined circuit nodes in a processing system. Test code which includes a set of software-controllable interrupts is executed using a multiple input shift register (MISR) to generate a MISR signature. One or more select... | 11/15/2011 |
| 8060724 | Provision of extended addressing modes in a single instruction multiple data (SIMD) data processor Executing a first memory access instruction with update by an N-bit processor includes accessing at least one source register of a plurality of registers, wherein the accessing includes accessing a first register, wherein each register of the plurality of registers ... | 11/15/2011 |
| 8051226 | Circular buffer support in a single instruction multiple data (SIMD) data processor A method is provided for generating a control vector. The method comprising: providing a circular buffer having a plurality of storage elements that are arranged sequentially from a designated first storage element to a designated last storage element, and when the ... | 11/01/2011 |
| 8048738 | Method for forming a split gate device A method for forming a semiconductor device includes forming a dielectric layer over a substrate. The method further includes forming a select gate layer over the dielectric layer. The method further includes etching the select gate layer at a first etch rate to for... | 11/01/2011 |
| 8044494 | Stackable molded packages and methods of making the same A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electri... | 10/25/2011 |
| 8042071 | Circuit and method for avoiding soft errors in storage devices A storage element within a circuit design is identified. The storage element is replaced with both a first storage cell and a second storage cell. The second storage cell operates as a redundant storage cell to the first storage cell. An output of the first storage ... | 10/18/2011 |
| 8040700 | Charge pump for use with a synchronous load A charge pump has circuitry and implements a method for monitoring a synchronous load by using a first voltage threshold below a target output voltage and a second voltage threshold above a target output voltage. An output terminal is coupled to the load. Charge is ... | 10/18/2011 |
| 8039386 | Method for forming a through silicon via (TSV) A method of forming a through silicon via includes forming a via opening in a substrate using a hard mask, wherein a polymer is formed in the via opening. A first wet clean removes a first portion of the polymer and forms a first carbon containing oxide along portio... | 10/18/2011 |
| 8039312 | Method for forming a capped micro-electro-mechanical system (MEMS) device A capped micro-electro-mechanical systems (MEMS) device is formed using a device wafer and a cap wafer. The MEMS device is located on a frontside of the device wafer. A frontside of a cap wafer is attached to the frontside of the device wafer. A first stressor layer... | 10/18/2011 |
| 8032030 | Multiple core system An integrated circuit has a group of cores that communicate with a packet switch using carrierless ultra wideband (UWB) radio frequency (RF) signaling. The packet switch communicates outside the integrated circuit using optical signaling. The carrierless UWB provide... | 10/04/2011 |
| 8030986 | Power transistor with turn off control and method for operating A circuit has a power transistor, a driver control circuit, a variable clamp circuit and a turn-off control circuit. The power transistor has a first current electrode coupled to a first power supply terminal, a second current electrode as an output of the circuit, ... | 10/04/2011 |
| 8026760 | Gain enhanced switched capacitor circuit and method of operation A switched capacitor circuit utilizes a pair of serially connected differential amplifiers that have plus inputs, minus inputs, plus outputs, and minus outputs. Feedback to the plus/minus inputs is in a first configuration relative to the output of the pair of diffe... | 09/27/2011 |
| 8021970 | Method of annealing a dielectric layer A method includes forming a first dielectric layer over a substrate; forming nanoclusters over the first dielectric layer; forming a second dielectric layer over the nanoclusters; annealing the second dielectric layer using nitrous oxide; and after the annealing the... | 09/20/2011 |
| 8010854 | Method and circuit for brownout detection in a memory system Detecting brown-out in a system having a non-volatile memory (NVM) includes loading data in the NVM, wherein a next step in loading is performed on a location in the NVM that is logically sequential to an immediately preceding loading. A pair of adjacent locations i... | 08/30/2011 |
| 8004907 | SRAM with read and write assist A memory includes an SRAM bitcell including a pair of cross-coupled inverters, wherein a first inverter of the pair includes a first device having a body and a second inverter of the pair includes a second device having a body. A first selection circuit has a first ... | 08/23/2011 |
| 8004080 | Edge mounted integrated circuits with heat sink A module has a substrate, first and second integrated circuits, and a heat sink. The integrated circuits each have a first major surface, a second major surface, a first edge, a second edge, and a third edge and have optical circuits having ports on the first edge a... | 08/23/2011 |
| 7992052 | Program correlation message generation for debug A data processing system and method includes a data processor and memory that are coupled to debug circuitry that generates debug messages including address translation trace messages. A memory management unit (MMU) includes a translation lookaside buffer (TLB) for ... | 08/02/2011 |
| 7990795 | Dynamic random access memory (DRAM) refresh A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one ... | 08/02/2011 |
| 7986189 | Amplifier with feedback A circuit includes a first resistive element coupled to a diode, a second resistive element, a first transistor having a first current electrode coupled the second resistive element, a second transistor having a first current electrode coupled to the first resistive... | 07/26/2011 |
| 7985655 | Through-via and method of forming In one embodiment, a method of forming a via includes providing a semiconductor substrate, wherein the semiconductor substrate comprises a through-via region, forming isolation openings and a sacrificial feature in the through-via region, filling the isolation openi... | 07/26/2011 |
| 7984337 | Address translation trace message generation for debug A data processing system and method generates debug messages by permitting an external debug tool to have real-time trace functionality. A data processor executes a plurality of data processing instructions and uses a memory for information storage. Debug circuitry ... | 07/19/2011 |
| 7945418 | Stream based stimulus definition and delivery via interworking An approach is provided to manage test transactors that interface with components of a hardware design. A first set of transactors is launched with the first set of transactors sending stimuli to various components that correspond to the first set of transactors. A ... | 05/17/2011 |
| 7937573 | Metric for selective branch target buffer (BTB) allocation A method and data processing system allocates entries in a branch target buffer (BTB). Instructions are fetched from a plurality of instructions and one of the plurality of instructions is determined to be a branch instruction. A corresponding branch target address ... | 05/03/2011 |
| 7927956 | Method for making a semiconductor structure using silicon germanium A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying t... | 04/19/2011 |
| 7925862 | Coprocessor forwarding load and store instructions with displacement to main processor for cache coherent execution when program counter value falls within predetermined ranges A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and... | 04/12/2011 |
