Bizarre Patents
A beach chair which can be adapted for a woman who is pregnant and wishes to sunbathe in the prone position.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 6230238 | Method and apparatus for accessing misaligned data from memory in an efficient manner A method and apparatus for performing mis-aligned read and write operations to a stack involves providing a memory array (110). The memory array is split into a high byte memory array (116) and a low byte memory array (112). Each memory array (112 and 116... | 05/08/2001 |
| 6169420 | Output buffer An output buffer (200) having a protection circuit (228, 230, 232) which adjusts control of an output drive circuit (224,226) in response to external voltages on the output pin (202). When the output pin is in a tri-state condition and receives an externa... | 01/02/2001 |
| 6160305 | Beta dependent temperature sensor for an integrated circuit A thermal sensing element (10) incorporates a vertical pnp bipolar transistor (12) whose BETA is dependent on temperature. This known relationship can be used to build a temperature sensor (200, 300), that is inexpensive, reliable, and whose process varia... | 12/12/2000 |
| 6131080 | Method of monitoring a computer simulation of an electrical circuit A simulation monitor (502) automatically generates a monitor file (510) from a static timer output file (504). The monitor file instantiates a function, a firing equation, that triggers if and only if a critical timing path also triggers. The monitor file... | 10/10/2000 |
| 6130821 | Multi-chip assembly having a heat sink and method thereof A multi-chip assembly (100) uses a clip (110) to retain multiple integrated circuits (124-130) to an assembly substrate (140). The use of a thermal medium between the integrated circuits and the heat sinks (120, 122) allows the assembly to be disassembled... | 10/10/2000 |
| 6108181 | Electrostatic discharge (ESD) circuit An electrostatic discharge (ESD) discharge circuit provides robust protection to an integrated circuit (13). In one embodiment, a resistive element (71) ensures that current shunting bipolar devices (60, 62, and 68) turn-on before devices within the integ... | 08/22/2000 |
| 6046897 | Segmented bus architecture (SBA) for electrostatic discharge (ESD) protection A segmented bus architecture (800) removes certain ESD circuitry from each I/O pad cell (806, 812) and places it in a power pad cell (808, 814) or in some other unused area of the integrated circuit which incorporates the SBA. The removed ESD circuit is s... | 04/04/2000 |
| 6029006 | Data processor with circuit for regulating instruction throughput while powered and method of operation A data processor (10) incorporates instruction regulating or "throttling" circuitry (31) for limiting consumed power. A user visible register maintains an INTERVAL field by which instruction fetch from an instruction cache (14) is periodically delayed. Th... | 02/22/2000 |
| 5963588 | Apparatus for modulating/demodulating signals An apparatus connects a data processing system (10) with an analog telephone line and/or an ISDN line. The apparatus modulates and demodulates data from the data processing system (10) to either of the two different telephone protocols without adding unne... | 10/05/1999 |
| 5956336 | Apparatus and method for concurrent search content addressable memory circuit A circuit and method is provided for implementing a content addressable memory circuit (100) in which an output word is produced which corresponds to the content of a reference word containing an ATM header. According to a first aspect, a binary search lo... | 09/21/1999 |
| 5917336 | Circuit for electrostatic discharge (ESD) protection An electrostatic discharge (ESD) circuit (700) provides robust protection to an input/output driver circuit (10). The discharge path is provided by a bipolar transistor (202). The bipolar device is triggered by a combination of an n-type MOSFET (702), a s... | 06/29/1999 |
| 5903419 | Circuit for electrostatic discharge (ESD) protection An electrostatic discharge (ESD) circuit (12) provides robust protection to an input/output driver circuit (10). The discharge path is provided by a parasitic bipolar transistor (202). The parasitic bipolar device is triggered by a combination of a MOSFET... | 05/11/1999 |
| 5893137 | Apparatus and method for implementing a content addressable memory circuit with two stage matching A circuit and method is provided for implementing a content addressable memory circuit (100) in which at least one output word is produced which corresponds to the content of a match word. A binary search logic circuit (103) binarily searches the memory a... | 04/06/1999 |
| 5892777 | Apparatus and method for observing the mode of a memory device A method and apparatus observes a mode register (102) in a synchronous memory device. A multiplexer (306) selects the value of the mode register (102) or the conventional data path of the memory array (302) through the output buffer. The invention outputs... | 04/06/1999 |
| 5859849 | Modular switch element for shared memory switch fabric A modular switch element (12) is programmable to operate in conjunction with varying numbers of other modular switch elements in a shared memory switch fabric (10). A single modular switch element type can be used to construct a range of shared memory swi... | 01/12/1999 |
| 5848025 | Method and apparatus for controlling a memory device in a page mode A method (600, 700) and apparatus (402) for controlling a memory device, such as a synchronous dynamic random access memory (404), includes a user-programmable register containing a new parameter, PRECHARGE DELAY TIME. A memory controller (402) uses the p... | 12/08/1998 |
| 5687349 | Data processor with branch target address cache and subroutine return address cache and method of operation A data processor (10) has a branch and link address cache (++ BLAC++) (40) and a Branch Target Address Cache (BTAC) (48) for storing a number of recently encountered fetch address-target address pairs. The BLAC buffers data pairs ide... | 11/11/1997 |
| 5668975 | Method of requesting data by interlacing critical and non-critical data words of multiple data requests and apparatus therefor A method of requesting data in a data processing system has the steps of receiving a plurality of requests for data by a request arbitrator (12) from a plurality of requesters (REQUESTER A, REQUESTER B, REQUESTER C), requesting a first portion of each req... | 09/16/1997 |
| 5664215 | Data processor with an execution unit for performing load instructions and method of operation The disclosed data processor (10) dispatches load/store multiple and load/store string instructions to a load/store unit (28) as a sequence of simple load or store instructions. The sequencer unit (18) assigns an entry of a rename buffer (34) to which the... | 09/02/1997 |
| 5649206 | Priority arbitration protocol with two resource requester classes and system therefor An arbitration protocol (68) comprises the steps of receiving a first (70) and a second (74) plurality of resource request signals, and either, granting the shared resource to a selected one of a first plurality of resource users (72) or granting the shar... | 07/15/1997 |
| 5646878 | Content addressable memory system A CAM system (2) stores a plurality of data sets in a plurality of pairs of CAM cells (4) and RAM cells (6). The portion of a particular data set stored in one of the RAM cells is accessed by inputting a tag to CAM cells that matches the portion of the da... | 07/08/1997 |
| 5642493 | Method of loading instructions into an instruction cache by repetitively using a routine containing a mispredicted branch instruction A method of loading a particular block of instructions into the instruction cache (14) of a Harvard architecture data processor (10) involves repetitively mis-predicting a branch instruction in a loop. The branch instruction is conditioned upon an instruc... | 06/24/1997 |
| 5636354 | Data processor with serially accessed set associative memory cache interface and method A memory cache interface (12) serially accesses each way in an M-way set asociative memory cache (11) when it performs a read operation. The memory cache returns a data quantum and a tag corresponding to each presented input. The memory cache interface pr... | 06/03/1997 |
| 5630095 | Method for use with a data coherency protocol allowing multiple snoop queries to a single snoop transaction and system therefor A method for use with a data coherency protocol has the steps of receiving a bus transaction in a data processor from a bus, receiving a first response from a memory location, .generating a first protocol signal, receiving a second response from the memor... | 05/13/1997 |
| 5627975 | Interbus buffer for use between a pseudo little endian bus and a true little endian bus An interbus buffer (18) coordinates data transfers between two different sized buses. The first bus (processor bus) allows data to be ordered according to either a big endian protocol or a "munged" little endian mode. The second bus (local bus) allows dat... | 05/06/1997 |
| 5621896 | Data processor with unified store queue permitting hit under miss memory accesses A store queue for use in a data processor (10) with a memory storage system has a first-in-first-out ("FIFO") queue (48) and control circuitry (52). The control circuitry maintains three pointers which index the entries in the FIFO queue: a dispatch point... | 04/15/1997 |
| 5613081 | Method of operating a data processor with rapid address comparison for data forwarding A data processor (10) has an execution unit (18, 20) for generating the address of each requested data double-word. The data processor fetches the entire memory line, four double-words of data, containing the requested double-word when the requested doubl... | 03/18/1997 |
| 5606682 | Data processor with branch target address cache and subroutine return address cache and method of operation A data processor (10) has a branch and link address cache ("BLAC") (40) and a BTAC (48) for storing a number of recently encountered fetch address-target address pairs. The BLAC buffers data pairs identifying corresponding subroutine call and subroutine r... | 02/25/1997 |
| 5604879 | Single array address translator with segment and page invalidate ability and method of operation A CAM/SRAM structure (44) performs address translations that are compatible with a segmentation/paging addressing scheme yet require only a single look-up step. Each entry in the effective-to-real-address-translator (ERAT) has two CAM fields (ESID, EPI) t... | 02/18/1997 |
| 5550974 | Testable memory array which is immune to multiple wordline assertions during scan testing A testable memory array (34) has a plurality of TAG-DATA field pairs. Each TAG asserts a MATCHLINE signal if an input tag matches a stored tag. During normal operation, the asserted matchline signal causes the entry to outputs its DATA field. During a tes... | 08/27/1996 |
| 5539892 | Address translation lookaside buffer replacement apparatus and method with user override A data processor (10) has a translation lookaside buffer, a "TLB," (56) for translating internal effective addresses into external real addresses. A user programmable bit in a special purpose register (68) controls which TLB entry in a group of entries wi... | 07/23/1996 |
| 5535351 | Address translator with by-pass circuit and method of operation An address translator (42) with a by-pass circuit (106) translates a received effective address into a real address in a first mode of operation by matching a portion of the effective address and a stored translation tag. The address translator outputs a ... | 07/09/1996 |
| 5535346 | Data processor with future file with parallel update and method of operation The disclosed data processor (10) has a future file (60) for providing the most recent value of a set of architectural registers (32, 36) to the various execution units (20, 22, 24, 26, 28, 30) of the data processor. The most recent value of the set of ar... | 07/09/1996 |
| 5530822 | Address translator and method of operation An address translator (126) translates addresses, acting like a register file or a table, as necessary. The address translator contains a number of entries for matching an input address to a stored tag. An entry outputs a stored translated address if its ... | 06/25/1996 |
| 5530825 | Data processor with branch target address cache and method of operation A data processor (10) has a BTAC (48) storing a number of recently encountered fetch address-target address pairs. Each pair also includes an offset tag identifying which one of a plurality of instructions indexed by the fetch address generated the entry.... | 06/25/1996 |
| 5530824 | Address translation circuit A CAM/SRAM structure (42) performs address translations of variable length blocks, a "block address translator." Each address translation is stored in a register broken into an upper half and a lower half. The upper half contains CAM bit cells (56) which ... | 06/25/1996 |
| 5508644 | Sense amplifier for differential voltage detection with low input capacitance A sense amplifier (10) has a pair of cross-coupled latches (12, 14, 16, 18) connected between a first voltage supply (VDD) and the sources of two transistors (20, 22). The gates of the two transistors receive a voltage differential to be sensed... | 04/16/1996 |
| 5500950 | Data processor with speculative data transfer and address-free retry A data processor with speculative data transfer has address circuitry (40) and data circuitry (42, 44). The address circuitry generates a memory address associated with a data block and with a tag. The tag is representative of the validity of the data blo... | 03/19/1996 |
| 5500943 | Data processor with rename buffer and FIFO buffer for in-order instruction completion A data processor has first calculation circuitry (26), a rename buffer (34), and a queue (36). The first calculation circuitry generates a first and a second result from supplied operands and received programmed instructions. The rename buffer is coupled ... | 03/19/1996 |
| 5499204 | Memory cache with interlaced data and method of operation A memory cache (14) has a plurality of cache lines (50) for storing a series of contiguous memory elements. Each series of memory elements are interlaced within the corresponding cache line on a element-by-element basis and on a bit-by-bit basis. This sto... | 03/12/1996 |
