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| Number | Title | Issue Date |
| 7945786 | Method and apparatus to re-create trust model after sleep state A processing system features random access memory (RAM), a processor, and a trusted platform module (TPM). When the processing system enters a sleep mode during which the RAM is to stay powered, the processing system may measuring a VMM and one or more secure VMs in... | 05/17/2011 |
| 7499043 | Switching of display refresh rates Some embodiments describe techniques that may relate to switching of display refresh rates. In one embodiment, modification of a display refresh rate may be initiated after the last pixel of a portion of a first image frame is driven. Other embodiments are also desc... | 03/03/2009 |
| 7496826 | Method, system, and apparatus for adjacent-symbol error correction and detection code A circuit and method for generating an Error Correcting Code (ECC) based on an adjacent symbol codeword that is formed in two clock phases among other techniques are described. In one embodiment, an apparatus is to comprise one or more logics to: generate a pluralit... | 02/24/2009 |
| 7495922 | Spring loaded heat sink retention mechanism Methods and apparatus to provide a spring loaded heat dissipative device retention mechanism are described. In one embodiment, one or more pins with spring portions are used to maintain a spring force between a heat dissipative device and a printed circuit board. Ot... | 02/24/2009 |
| 7495623 | Modular waveguide inteconnect In some embodiments, an electronic device comprises a circuit board, an antenna structure on the circuit board, and a waveguide mounted on the circuit board above the antenna structure. Other embodiments may be described. ... | 02/24/2009 |
| 7486724 | Codec compensation techniques for channel analysis applications Methods and apparatus to perform and/or analyze communication channels are described. In one embodiment, a test signal may be generated and transferred using a first signal route to a line-under-test in response to line qualification mode. The first signal route may... | 02/03/2009 |
| 7484045 | Store performance in strongly-ordered microprocessor architecture A store operation architecture in which store operation latency and read-for-ownership (RFO) throughput are improved. Embodiments of the invention relate to a method and apparatus to improve store performance in a microprocessor by allowing out-of-order issuance of ... | 01/27/2009 |
| 7480781 | Apparatus and method to merge and align data from distributed memory controllers We describe a system and method to merge and align data from distributed memory controllers. A memory system includes a command bus to transmit a predetermined memory access command, and a memory interface to manipulate data from at least two memory channels, each m... | 01/20/2009 |
| 7478212 | Techniques to transfer information between memory regions Techniques are described herein that may be used to de-fragment a first region of memory. For example, de-fragmenting may include identifying multiple accessed memory locations in the first memory region; and copying the accessed memory locations using the data move... | 01/13/2009 |
| 7472299 | Low power arbiters in interconnection routers Methods and apparatus to reduce power consumption in arbiters of interconnection routers are described. In one embodiment, an arbiter may be turned off for a select number of clock cycles if no arbitration is to be performed on the corresponding buffer. ... | 12/30/2008 |
| 7461142 | Method and apparatus for address management in a network device Numerous embodiments of a method and apparatus for address management in a network device are disclosed. ... | 12/02/2008 |
| 7457924 | Hierarchical directories for cache coherency in a multiprocessor system Use of an import cache and/or an export directory with an agent within to respond to requests for data. The import cache stores data that has been imported through the agent. The export directory stores information related to data that has been exported through the ... | 11/25/2008 |
| 7434006 | Non-speculative distributed conflict resolution for a cache coherency protocol A conflict resolution technique provides consistency such that all conflicts can be detected by at least one of the conflicting requestors if each node monitors all requests after that node has made its own request. If a line is in the Exclusive, Modified or Forward... | 10/07/2008 |
| 7428056 | Method and apparatus for optically analyzing a surface A method and apparatus for analyzing a surface of a test object employs apparatus with a scanning interferometry system which generates a windowed interferometric signal from the surface of a test object to characterize the surface of the test object. ... | 09/23/2008 |
| 7426215 | Method and apparatus for scheduling packets A method and apparatus for scheduling packets using a pre-sort scheduling array having one or more smoothing registers. The scheduling array includes a number of round buffers, each round buffer having an associated smoothing register. To schedule a packet for trans... | 09/16/2008 |
| 7423264 | Atomic force microscope In one embodiment, an atomic force microscope comprises a frame, a beam coupled to the frame at a first end and a second end, a probe mounted to the beam, means for inducing relative motion between the beam and an underlying surface, and means for detecting a charac... | 09/09/2008 |
| 7415658 | Forward error correction mapping and de-mapping techniques Briefly, techniques to provide varying levels of enhanced forward error correction without modifying a line rate of a frame. ... | 08/19/2008 |
| 7408649 | Method and apparatus for optically analyzing a surface Apparatus and methods are provided for analyzing surface characteristics of a test object using broadband scanning interferometry. Test objects amenable to these apparatus and methods include but are not limited to semiconductor wafers, semiconductor devices, metall... | 08/05/2008 |
| 7400033 | Package on package design to improve functionality and efficiency Methods and apparatus to provide an improved package on package (PoP) design are described. In one embodiment, a central processing unit (CPU) package substrate and an embedded package (which may include one or more heat removal channels) are molded. Other embodimen... | 07/15/2008 |
| 7397621 | Servo pattern characterization on magnetic disks In one embodiment, a surface analyzer system comprises a radiation targeting assembly to target radiation onto a surface, a reflected radiation collecting assembly that collects radiation reflected from the surface, and a signal processing module. The signal process... | 07/08/2008 |
| 7397553 | Surface scanning In one embodiment, a surface scanning system comprises a radiation directing assembly that scans a surface using a Cartesian scanning pattern; and a radiation collecting assembly that collects radiation reflected from the surface. A scattered radiation collection sy... | 07/08/2008 |
| 7396022 | System and method for optimizing wafer flatness at high rotational speeds The present invention is a chuck having a vacuum groove that is capable of holding a wafer as the chuck rotates on a spindle. As the chuck rotates the air pressure above the center of the wafer is reduced. In order to reduce the bowing of the wafer that can result f... | 07/08/2008 |
| 7394809 | Method and apparatus for packet classification using a forest of hash tables data structure A packet classifier having a forest of hash tables data structure. The forest of hash tables data structure includes a number of hash tables, each hash table having a bit mask corresponding to an equivalent set of rules. Each hash table includes a number of entries,... | 07/01/2008 |
| 7395485 | Check codes mapped across multiple frames Memory apparatus and methods transmit or receive a first portion of a check code in a first frame and a second portion of the check code in a second frame. The check code may be for all or a portion of the first frame, the second frame, or any other frame. Other emb... | 07/01/2008 |
| 7386768 | Memory channel with bit lane fail-over Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plura... | 06/10/2008 |
| 7383399 | Method and apparatus for memory compression Memory apparatus and methods for memory compression. A memory agent may comprise a compression engine to compress or decompress data in the agent without sending the data on the host memory channel. Other embodiments are described and claimed. ... | 06/03/2008 |
| 7380180 | Method, system, and apparatus for tracking defective cache lines To facilitate a processor during a reset operation, a linked list of pointers to a list of defective cache lines is created. The good data bits in defective cache lines are used for creating a linked list or other data structure for storing relevant information rega... | 05/27/2008 |
| 7366153 | Apparatus and method capable of providing quality of service channel access in a wireless network Briefly, in accordance with one embodiment of the invention, an apparatus with capabilities to communicate in a wireless network, comprising a channel access scheme providing access to the wireless network, the access scheme using a modulo N backoff scheme providing... | 04/29/2008 |
| 7366470 | Inter-modulation distortion compensation An Inter-modulation distortion measurement and correction method which could be applied over a communication channel that is a combination of either or both analog and digital channels. This method is applicable for a communication system between a modem pair. ... | 04/29/2008 |
| 7362425 | Wide spatial frequency topography and roughness measurement In one embodiment, a system to inspect a surface comprises an assembly to direct a first radiation beam onto a surface in a first plane of incidence, a first detector to generate a first signal from a portion of the radiation reflected from the first radiation beam,... | 04/22/2008 |
| 7362839 | Techniques to adjust vertical offset Techniques to modify bias levels of a limiting amplifier based on a transition measurement and measurements before and after the transition. ... | 04/22/2008 |
| 7355711 | Method for detecting an end-point for polishing a material An optical surface analysis system for scanning the surface of a (silicon) wafer and detect if any residual material is still on the wafer surface in order to determine an appropriate end-point in a polishing process. An Optical Surface Analyzer (OSA), of the presen... | 04/08/2008 |
| 7353338 | Credit mechanism for multiple banks of shared cache Methods and apparatus to manage credits in a computing system with multiple banks of shared cache are described. In one embodiment, a credit request from a processor core is translated into a physical credit that corresponds to one of the multiple banks of shared ca... | 04/01/2008 |
| 7349353 | Techniques to reduce echo Briefly, techniques to control echo that utilize fixed and adaptive filters are described. ... | 03/25/2008 |
| 7346883 | System and method for integrated data transfer, archiving and purging of semiconductor wafer data A system for the integrated archiving, restoring, purging, importing and exporting of semiconductor wafer data, the system including a data acquisition system for acquiring scan data from differing types of semiconductor wafer scanning tools such as wafer dimensiona... | 03/18/2008 |
| 7345751 | Material independent optical profilometer A system and method for measuring defects, film thickness, contamination, particles and height of a thin film disk or a silicon wafer. The system includes a processor for determining height. In addition to measuring the height the system can measure film thickness a... | 03/18/2008 |
| 7346825 | Error method, system and medium Error detection methods, systems and medium are provided. The error detection method may comprise processing error conditions associated with transactions in a manner that may enable error source identification. The system may comprise a plurality of nodes of compon... | 03/18/2008 |
| 7343583 | System and method for searching for patterns of semiconductor wafer features in semiconductor wafer data A system for the integrated archiving, restoring, purging, importing and exporting of semiconductor wafer data, the system including a data acquisition system for acquiring scan data from differing types of semiconductor wafer scanning tools such as wafer dimensiona... | 03/11/2008 |
| 7342883 | Method and apparatus for managing network traffic Numerous embodiments of a method and apparatus for managing network traffic are disclosed. ... | 03/11/2008 |
| 7339786 | Modular server architecture with Ethernet routed across a backplane utilizing an integrated Ethernet switch module A modular server system includes a midplane having a system management bus and a plurality of blade interfaces on the midplane. The blade interfaces are in electrical communication with each other. A server blade is removeably connectable to one of the plurality of ... | 03/04/2008 |
