Did You Know...
...Chester Carlson was a patent agent who tired of having to make multiple copies of patent applications using the only duplication method available at the time: carbon paper. In 1959 he came up with a new copying system and took it to IBM for evaluation. The "experts" at IBM determined potential sales to be only 5,000 units because people wouldn't want to use a bulky machine when they had carbon paper. Carlson's invention was the xerography process, the company founded on the system is Xerox.
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| Number | Title | Issue Date |
| 7392441 | Method of performing operational validation with limited CPU use of a communications network A system, apparatus, computer program product and method of performing operational validation on a system are provided. The system may include a CPU with a cache, a communications network, and a plurality of devices exchanging data during a test. When the test is re... | 06/24/2008 |
| 7386759 | Method of performing functional validation testing A system, apparatus, computer program product and method of performing functional validation testing in a system are provided. Generally, functional validation testing includes data acquisition and data validation testing. During the functional validation testing tw... | 06/10/2008 |
| 7376875 | Method of improving logical built-in self test (LBIST) AC fault isolations A system, apparatus and method of isolating a plurality of limiting logical cones in a chip during a logical built-in self test (LBIST) are provided. An LBIST is performed on the chip in order to locate a first latch that fails the test. Particularly, latches on the... | 05/20/2008 |
| 7275199 | Method and apparatus for a modified parity check A method, an apparatus, and a computer program are provided for sequentially determining parity of stored data. Because of the inherent instabilities that exist in most memory arrays, data corruption can be a substantial problem. Parity checking and other techniques... | 09/25/2007 |
| 7242233 | Simplified method for limiting clock pulse width The present invention provides for correcting excessive pulse widths using incremental delays. The pulse width is evaluated through a correction block and leak detector. An acceptable pulse passes through an interconnect directly to the clock output. Unacceptable pu... | 07/10/2007 |
| 7243195 | Software managed cache optimization system and method for multi-processing systems The present invention provides for a method for computer program code optimization for a software managed cache in either a uni-processor or a multi-processor system. A single source file comprising a plurality of array references is received. The plurality of array... | 07/10/2007 |
| 7170328 | Scannable latch A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signal... | 01/30/2007 |
| 7170316 | Programmable logic array latch A programmable logic array (PLA) latch is disclosed. The PLA latch includes a first logic array, a second logic array and only one output latch. The second logic array is coupled to the first logic array. The output latch is coupled to the second logic array. ... | 01/30/2007 |
| 7171563 | Method and system for ensuring security of code in a system on a chip The present invention provides for validating downloaded code. Code is transferred to a volatile memory of a system on a chip from a source. The volatile memory is decoupled from the source of the transferred code through employment of an isolation bus. An embedded ... | 01/30/2007 |
| 7165006 | Scan chain disable function for power saving An apparatus, a method and a computer program product are provided for conserving energy during functional mode of a processor by disabling the scan chain. By inserting logic gating into the scan chain it is possible to disable the scan chain during the processor's ... | 01/16/2007 |
| 7155493 | Method and apparatus for improved internet navigation A monitor analyzes and generates a profile of an Internet website data transmission. The profile indicates the relative load and/or execution times of different components of the data, including text, images, and Java code. The profile is displayed and an end-user d... | 12/26/2006 |
| 7133320 | Flood mode implementation for continuous bitline local evaluation circuit A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood m... | 11/07/2006 |
| 7130947 | Method of arbitration which allows requestors from multiple frequency domains The present invention provides a method of arbitration for resources which allows requestors from multiple frequency domains. Most requestors generate requests at full speed. A small number of low-speed requesters generate requests every two full-speed cycles, and h... | 10/31/2006 |
| 7114042 | Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment The present invention provides for atomic update primitives in an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA transfers. At least one lock line command is generated from a set comprising a get lock line command... | 09/26/2006 |
| 7113881 | Method and apparatus for semi-automatic extraction and monitoring of diode ideality in a manufacturing environment A method, an apparatus, and a computer program are provided for the semi-automatic extraction of an ideality factor of a diode. Traditionally, current/voltage curves for diodes, which provided a basis for extrapolating the ideality factors, had to be determined by h... | 09/26/2006 |
| 7093029 | Method and system for providing accessibility to electronic mail A method and system that provide an accessibility gateway to Internet e-mail through the use of a web intermediary server. The web intermediary server preferably includes server-generated applications for modifying accessibility settings for supported client devices... | 08/15/2006 |
| 7090358 | System, apparatus and method of displaying information for foveal vision and peripheral vision A system, apparatus and method of displaying information for foveal vision and peripheral vision are provided. The system, apparatus and method generate a composite display image fully viewable with foveal vision and peripheral vision. The system, apparatus and meth... | 08/15/2006 |
| 7062547 | Method and system for providing a central repository for client-specific accessibility A method and system that provide a central repository for client specific accessibility applications to a user from an accessible server. The repository is updated on a periodic basis with new solutions provided by the service provider, who also manages licensing ag... | 06/13/2006 |
| 7035958 | Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the target A method of operating a request FIFO of a system on a chip (SoC) in which a requests in a first position that has been granted and which subsequently receives a retry from the intended target is automatically re-ordered with respect to the other requests below it in... | 04/25/2006 |
| 7010581 | Method and system for providing browser functions on a web page for client-specific accessibility A method and system that provide browser-based functions by injected into a web page a control button, form text field or similar browser-based function control such that both the browser controls and the content of the web page can be transformed for accessibility.... | 03/07/2006 |
| 7003064 | Method and apparatus for periodic phase alignment In one form, apparatus for aligning clock signals includes first and second logic circuitry for receiving respective first and second clock signals. The first and second clock signals are substantially synchronized and operations of the first logic circuitry and sec... | 02/21/2006 |
| 6985972 | Dynamic cache coherency snooper presence with variable snoop latency A data processing system with a snooper that is capable of dynamically enabling and disabling its snooping capabilities (i.e., snoop detect and response). The snooper is connected to a bus controller via a plurality of interconnects, including a snooperPresent signa... | 01/10/2006 |
| 6970918 | System and method for transcoding support of web content over secure connections A method and system using for establishing an intermediary connection between a client device and a secure website using a web proxy machine. In the preferred embodiment, a secure connection is established between the web proxy and the secure content server. A respo... | 11/29/2005 |
| 6961759 | Method and system for remotely managing persistent state data A system for removing and saving in an intermediary web server Internet cookies being transmitted from a web content server to a client device. Internet cookies, being persistent client data for a specific user and a specific content provider, typically contain sens... | 11/01/2005 |
| 6944665 | Method and system for delivering accessibility using a distributed environment A method and system that provide an accessibility gateway to the Internet through the use of a web intermediary server, which may belong to a different domain than the web content server. The web intermediary server includes server-generated applications for modifyi... | 09/13/2005 |
| 6928533 | Data processing system and method for implementing an efficient out-of-order issue mechanism An out-of-order issue mechanism for a data processing system allows two out-of-order instructions to be issued to independent “pipes” from a window of four instructions currently queued for execution. If the two pipes execute floating pipe operations, dependenci... | 08/09/2005 |
| 6915415 | Method and apparatus for mapping software prefetch instructions to hardware prefetch logic A method and apparatus for mapping some software prefetch instructions in a microprocessor system to a modified set of hardware prefetch instructions and executing the software prefetch by invoking the corresponding modified hardware prefetch instruction. For common... | 07/05/2005 |
| 6907502 | Method for moving snoop pushes to the front of a request queue A method for prioritizing snoop pushes in a data processing system that schedules requests within a request FIFO. Each new request that is received is placed in the last position of the request FIFO and the request FIFO typically grants request based solely on the o... | 06/14/2005 |
| 6901003 | Lower power and reduced device split local and continuous bitline for domino read SRAMs A method, an apparatus, and a computer program are provided to reading indicia from an SRAM cell. A low value is generated on a write true line. A high value is generated on a continuous bit_line. The true node of the SRAM cell is evaluated through use of a floating... | 05/31/2005 |
| 6898675 | Data received before coherency window for a snoopy bus Where a null response can be expected from devices snooping a load operation, data may be used by a requesting processor prior to the coherency response window. A null snoop response may be determined, for example, from the availability of the data without a bus tra... | 05/24/2005 |
| 6898562 | Method and system for efficiently overriding net values in a logic simulator machine A method and system are described in a logic simulator machine for overriding a value of a net during execution of a test routine. A model of a logic design to be simulated is built utilizing the logic simulator machine. The logic design includes multiple nets. One ... | 05/24/2005 |
| 6898135 | Latch type sense amplifier method and apparatus Disclosed is an apparatus for and a method of overcoming signal delay problems in a read-out path occurring in connection with pipelined memory circuits. A latch type sense amplifier (SA) is used to receive the memory cell logic levels during a pre-charge state in a... | 05/24/2005 |
| 6895454 | Method and apparatus for sharing resources between different queue types A method and an apparatus for sharing a request queue between two or more destinations. The method and apparatus utilizes a common data table and a common age queue. The age queue is used to select the oldest request. The corresponding request from the common data t... | 05/17/2005 |
| 6886106 | System and method for controlling a multiplexer for selecting between an input clock and an input duty-cycle-corrected clock and outputting the selected clock and an enable signal A method and apparatus for providing a dynamically alterable output clock from an input clock based on the value of an integer, where the integer can be modified continuously. The invention also provides a sample cycle output which is an enable pulse, having the wid... | 04/26/2005 |
| 6885596 | Apparatus and method of wordline/bitline redundancy control using shift registers in an SRAM A decoder for use in wordline/bitline redundancy control is disclosed. In one aspect, the decoder includes first and second wordlines respectively coupled to redundant first and second wordlines, where the first and second wordlines are configured to be activated ba... | 04/26/2005 |
| 6880014 | Method and system of use of transcode directives for distributed control of transcoding servers A method and system using directive script in a web intermediary proxy machine that provides the function of a transcoder. The intermediary machine's transcoders are controlled by directive script that directs the order and properties of transcoder operations execut... | 04/12/2005 |
| 6879928 | Method and apparatus to dynamically recalibrate VLSI chip thermal sensors through software control The present invention provides an integrated circuit VLSI temperature system for the calibration of threshold temperatures. A temperature sensitive ring oscillator (TSRO) generates a TSRO calibration parameter. A memory is employable to store the TSRO calibration pa... | 04/12/2005 |
| 6876088 | Flex-based IC package construction employing a balanced lamination The present invention provides for a balanced laminated integrated circuit package. The package includes a two metal layer bumped circuit, a first adhesive layer having a thickness on a first side of the bumped circuit, a first outer conductive layer having a thickn... | 04/05/2005 |
| 6867121 | Method of apparatus for interconnecting a relatively fine pitch circuit layer and adjacent power plane(s) in a laminated construction The present invention provides for a method of interconnecting a bumped circuit having relatively fine traces to an overlying conductive layer of a laminated circuit assembly. The overlying conductive layer is laminated with a suitable insulating adhesive over a bum... | 03/15/2005 |
| 6865722 | Method of automating chip power consumption estimation calculation An apparatus, system and method of automatically computing power consumption estimation of a chip are provided. The apparatus, system and method include determining all circuit blocks or macros embedded in the chip and retrieving from a file, into which pre-generate... | 03/08/2005 |
