Quotables
"Inventing is a combination of brains and materials. The more brains you use, the less material you need."
Charles Kettering
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8178962 | Semiconductor device package and methods of manufacturing the same A semiconductor device package and methods of manufacturing the same are described. In some examples, a semiconductor device includes an IC die including a ring of die pads around a periphery thereof, lands disposed within the ring of die pads, bond terminals couple... | 05/15/2012 |
| 8176461 | Design-specific performance specification based on a yield for programmable integrated circuits A method for generating a design-specific timing specification includes inputting a first timing specification of a target device corresponding to a first timing yield. The first timing specification contains timing delays of elements located in at least first and s... | 05/08/2012 |
| 8176449 | Inference of hardware components from logic patterns The present invention provides a simplified process for inference using a generic logic pattern corresponding to one or more generic functions provided by the hardware component. A circuit design is mapped into a plurality of interconnected hardware components, and ... | 05/08/2012 |
| 8174112 | Integrated circuit device with low capacitance and high thermal conductivity interface An integrated circuit device includes an integrated circuit formed in a semiconductor die and an integrated circuit package containing the semiconductor die. The integrated circuit package includes a thermal interface material substantially between the semiconductor... | 05/08/2012 |
| 8146041 | Latch based optimization during implementation of circuit designs for programmable logic devices A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed u... | 03/27/2012 |
| 8146040 | Method of evaluating an architecture for an integrated circuit device A method of evaluating an architecture for an integrated circuit device is disclosed. The method comprises generating a library of primitives for a predetermined architecture; transforming an original dataflow program into an intermediate format; transforming the in... | 03/27/2012 |
| 8143695 | Contact fuse one time programmable memory A fuse structure for a semiconductor integrated circuit (IC) can include a first node comprising a region of a metal layer of an IC manufacturing process and a second node comprising a region of a conductive layer residing on a layer of the IC manufacturing process ... | 03/27/2012 |
| 8143532 | Barrier layer to prevent conductive anodic filaments A through hole is formed in a circuit board that has fibers dispersed in a polymer matrix. Copper is sputtered within the through hole to form a sufficiently conductive layer for electrolytic plating over the sputtered copper layer. ... | 03/27/2012 |
| 8127262 | Communicating state data between stages of pipelined packet processor Approaches for generating a specification of a pipelined packet processor. A textual specification includes input and output packet formats, each specifying a format for each field in the packet and a plurality of actions for processing one or more fields of an inpu... | 02/28/2012 |
| 8122420 | Congestion elimination using adaptive cost schedule to route signals within an integrated circuit A computer-implemented method of routing a circuit design for a target integrated circuit (IC) can include determining a characterization of routing congestion of the circuit design within the target IC and determining a first order cost component of using routing r... | 02/21/2012 |
| 8122414 | Placeholder-based design flow for creating circuit designs for integrated circuits Within a system comprising a processor and a memory, a method of creating a circuit design for implementation within an integrated circuit can include inserting a placeholder block into the circuit design, wherein the circuit design includes a circuit block comprisi... | 02/21/2012 |
| 8121826 | Graphical user interface for system design A design tool for designing a system includes a display device with a first visualization pane showing a symbolic representation of a connection between a first port and a second port of the system and a second visualization pane showing an unconnected port of the s... | 02/21/2012 |
| 8117580 | Multiple bitstreams enabling the use of partially defective programmable integrated circuits while avoiding localized defects therein Memory devices and data structures including multiple configuration bitstreams for programming integrated circuits (ICs) such as programmable logic devices (PLDs), thereby enabling the utilization of partially defective ICs. A user design is implemented two or more ... | 02/14/2012 |
| 8117247 | Configurable arithmetic block and method of implementing arithmetic functions in a device having programmable logic A configurable arithmetic block in a device having programmable logic for implementing arithmetic functions is disclosed. The configurable arithmetic block comprises a plurality of input registers coupled to receive multiple bit words; an arithmetic function circuit... | 02/14/2012 |
| 8115512 | Method and apparatus for dynamically aligning high-speed signals in an integrated circuit A method and apparatus for dynamically aligning high-speed signals in an integrated circuit are disclosed. For example, an integrated circuit according to one embodiment includes a logic fabric and at least one input/output interface coupled to the logic fabric. The... | 02/14/2012 |
| 8102188 | Method of and system for implementing a circuit in a device having programmable logic A method of implementing a circuit in a device having programmable resources and a predetermined amount of available internal memory is disclosed. The method comprises configuring the programmable resources of the device with a circuit design; storing a first page o... | 01/24/2012 |
| 8091060 | Clock domain partitioning of programmable integrated circuits A computer-implemented method of partitioning a circuit design into clock domains for implementation within a programmable integrated circuit (IC) can include storing a plurality of constraints that depend upon a plurality of variables, wherein the plurality of cons... | 01/03/2012 |
| 8091057 | Synthesis, place, and route responsive to reasons for critical paths not meeting performance objective Methods are provided for implementing a design of an integrated circuit meeting a performance objective. A timing analysis for the design specifies critical timing paths that do not meet the performance objective. Reasons are determined for the critical timing paths... | 01/03/2012 |
| 8090758 | Enhanced multiplier-accumulator logic for a programmable logic device A multiplier-accumulator includes a pre-adder, a multiplier, an accumulator, multiplexing logic, and control logic. The pre-adder is configured to sum a first input and a second input to produce a pre-sum output. The multiplier is configured to multiply a third inpu... | 01/03/2012 |
| 8090567 | Self-disabling simulation models using limits on assertions Approaches for managing a simulation model. A processor-implemented method includes simulating an electronic system using the simulation model and a simulator. The simulation model includes an assertion test that has an associated limit. The simulator counts a numbe... | 01/03/2012 |
| 8082535 | Method and apparatus for testing programmable integrated circuits A method of testing an IC generates a test design list of test patterns and produces an arc usage string for each test pattern. The arc usage strings are ranked according to the number of untested arcs in each successive test pattern by comparing each of the remaini... | 12/20/2011 |
| 8082530 | Power estimation in high-level modeling systems A computer-implemented method of estimating power usage for high-level blocks of a high-level modeling system (HLMS) circuit design can include generating a low-level circuit design from the HLMS circuit design. The method can include simulating the low-level circui... | 12/20/2011 |
| 8082527 | Representing the behaviors of a packet processor Methods are provided for compactly representing behaviors of a processor of packets. A declarative description of the processor is input. The declarative description specifies rules for manipulating the packets. A dependency graph is generated from the declarative d... | 12/20/2011 |
| 8082462 | Direct synthesis of audio clock from a video clock via phase interpolation of a dithered pulse An embodiment of the invention relates to a clock signal generator and a related method to produce a clock signal that is a rational but non-integer submultiple of a reference clock signal by employing a dithered pulse signal and a fractional phase signal. The ratio... | 12/20/2011 |
| 8082139 | Displaying signals of a design block emulated in hardware co-simulation Methods and systems for simulating an electronic system in a high level modeling system (HLMS). A design block and certain signals of the electronic system are selected. The selected signals include internal signals of the design block that are not ports of the desi... | 12/20/2011 |
| 8065648 | Method and apparatus for modeling an integrated circuit in a computer aided design system Method, apparatus, and computer readable medium for modeling an integrated circuit in a computer aided design system (CAD) are described. In some examples, a device model of the integrated circuit is generated in at least one first computer file, the device model ha... | 11/22/2011 |
| 8065644 | Reducing susceptibility of circuit designs to single event upsets A computer-implemented method of reducing susceptibility of a circuit design to single event upsets can include determining a susceptibility level of the circuit design to single event upsets, comparing the susceptibility level with a target susceptibility, and sele... | 11/22/2011 |
| 8065642 | Isolation verification for implementing modular redundancy within programmable integrated circuits A computer-implemented method of verifying isolation of a plurality of instances of a redundant module of a circuit design that is implemented within a single, programmable integrated circuit can include counting component failures needed to establish a connection b... | 11/22/2011 |
| 8065130 | Method for message processing on a programmable logic device Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of an integrated circuit is configured to have a plurality of thread circuits and a memory. Messages are received to th... | 11/22/2011 |
| 8063654 | Apparatus and method for testing of stacked die structure An integrated circuit device includes a stacked die and a base die having probe pads that directly couple to test logic of the base die to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts disposed on a back ... | 11/22/2011 |
| 8041855 | Dual-bus system for communicating with a processor A system for communicating with a processor within an integrated circuit can include a dual-bus adapter (115) coupled to the processor (105) through a first communication channel (110) and a second communication channel (120). The dual-bu... | 10/18/2011 |
| 8022724 | Method and integrated circuit for secure reconfiguration of programmable logic Approaches for secure configuration of a programmable logic integrated circuit (IC). In one approach, a method includes programming configuration memory of the programmable logic IC with a first configuration bitstream. At least a portion of a second configuration b... | 09/20/2011 |
| 8020131 | Method and apparatus for mapping flip-flop logic onto shift register logic Method and apparatus for mapping flip-flop logic onto shift register logic is described. In one example, a method of processing flip-flop logic in a circuit design for implementation in an integrated circuit is provided. A chain of flip-flops in the circuit design i... | 09/13/2011 |
| 8015537 | Automated rate realization for circuit designs within high level circuit implementation tools A computer-implemented method of automatic rate realization for implementing a circuit design within a programmable integrated circuit can include comparing data rates of clock domains of the circuit design with frequencies of available clock sources of the circuit ... | 09/06/2011 |
| 8015535 | Run-time efficient methods for routing large multi-fanout nets A method of limiting the routing resources of an integrated circuit (IC) that are available for use when routing multi-fanout nets can include selecting a multi-fanout net comprising a source and a plurality of loads and identifying each region of the IC which does ... | 09/06/2011 |
| 8015530 | Method of enabling the generation of reset signals in an integrated circuit A method of enabling the generation of reset signals in an integrated circuit is disclosed. The method comprises receiving information related to reset ports for a plurality of intellectual property cores in a design tool; providing an intellectual property core com... | 09/06/2011 |
| 8010923 | Latch based optimization during implementation of circuit designs for programmable logic devices A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed u... | 08/30/2011 |
| 8005881 | Scalable architecture for rank order filtering A rank order filter and instantiation thereof in programmable logic is described. A maximum filter core frequency is determined for an input sampling frequency, a filter window height, and a number of input samples. The maximum filter core frequency is greater than ... | 08/23/2011 |
| 8001511 | Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second ... | 08/16/2011 |
| 8001504 | Determining clock skew between nodes of an integrated circuit A set of respective first delay values for paths from a clock source to nodes of the integrated circuit is generated. Respective second delay values for the paths are generated from the clock source through the clock tree to the nodes. Each first delay value corresp... | 08/16/2011 |
