Famous Patents
The first match was accidentally discovered in 1826 when John Walker scraped a stick with chemicals on the end against a stone floor.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 6093588 | Process for fabricating a high voltage MOSFET A high-voltage lateral MOSFET transistor structure constituted by various interdigitated modular elements formed on a layer of monocrystaline silicon is described together with a process for its fabrication. To save area of silicon and to reduce the specific r... | 07/25/2000 |
| 5959465 | Fast Nor-Nor PLA operating from a single-phase clock A method is provided for operating a programmable logic array in an integrated circuit. Each stage of the circuit is enabled only during the time necessary for that stage to propagate an incoming signal. Enable signals are generated for the stages of the ... | 09/28/1999 |
| 5939768 | Vertical bipolar power transistor with an integrated sensing circuit A vertical structure, integrated bipolar transistor incorporating a current sensing resistor, comprises a collector region, a base region overlying the collector region, and an emitter region over the base region. The emitter region comprises a buried reg... | 08/17/1999 |
| 5936471 | Frequency compensation of a current amplifier in MOS technology The present invention relates to a current amplifier including a first MOS transistor with a drain defining a first terminal for controlling the amplifier with a current and a source connected to a first supply line. It also includes a second MOS transist... | 08/10/1999 |
| 5929766 | Device for controlling semiconductor wafer transport cassettes The invention relates to a dimensional control device for semiconductor wafer transport cassettes. Each cassette has a base from which extend vertical walls including horizontal grooves designed to receive wafers by lateral insertion. The device includes ... | 07/27/1999 |
| 5920505 | Negative word line voltage regulation circuit for electrically erasable semiconductor memory devices A negative word line voltage regulation circuit integratable in an electrically erasable semiconductor memory device. The circuit regulates a negative word line voltage to be supplied to word lines of the memory device during an electrical erasure of the ... | 07/06/1999 |
| 5918221 | Fuzzy analog processor with temperature compensation The analog processor can carry out processings independently of the operating temperature and process parameters, in a reliable manner and at high performance levels using fairly simple circuitry. To achieve this independence, the processor is basically i... | 06/29/1999 |
| 5894146 | EEPROM memory cells matrix with double polysilicon level and relating manufacturing process A matrix of EEPROM memory cells having a double polysilicon level of MOS technology and being arranged into rows and columns is monolithically integrated on a substrate of semiconductor material. Each cell comprises, in series, a transistor of the floatin... | 04/13/1999 |
| 5886945 | Circuit and method to adjust memory timing The circuit includes a memory element connected to an enabling input receiving an enabling signal, and in turn including a first reset circuit receiving an internal reset signal, and a second reset circuit receiving an external timing control signal, to g... | 03/23/1999 |
| 5867504 | Semiconductor memory device with row and column redundancy circuits and a time-shared redundancy circuit test architecture. A semiconductor memory device comprising redundancy memory elements for functionally replacing defective memory elements, redundancy circuits for operating said functional substitution of the redundancy memory elements for the defective memory elements, a... | 02/02/1999 |
| 5864562 | Circuit for transferring redundancy data of a redundancy circuit inside a memory device by means of a time-shared approach In a memory device equipped with a redundancy circuit comprising at least one redundancy memory register storing a defective address of a defective memory element and an identifying code suitable for identifying a portion of a matrix of memory elements wh... | 01/26/1999 |
| 5844851 | Anti-noise and auto-stand-by memory architecture Spurious memory readings which may be caused by noise induced by transitions in the output buffers of a fast parallel memory device are prevented by permitting output latches to change state in function of newly extracted data signals by means of an enabl... | 12/01/1998 |
