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| Number | Title | Issue Date |
| 8138888 | System and method for adjusting a seat using biometric information A method for adjusting a seat that includes one or more adjustable physical features includes for each person within a plurality of persons, calibrating the seat by determining a preferred setting for each of the one or more adjustable physical features of the seat;... | 03/20/2012 |
| 8073288 | Rendering a mask using coarse mask representation A method, system and computer program product for rendering a mask are disclosed. A method of rendering a mask may comprise: providing an initial mask design for a photolithographic process, the initial mask design including polygons; initially rendering the initial... | 12/06/2011 |
| 8019166 | Image data compression method and apparatuses, image display method and apparatuses The image data compression method involves the performing of steps: a block dividing step for dividing a computer processor pipeline statistic image to be displayed into a plurality of blocks with predetermined block width and block height; a block list creating ste... | 09/13/2011 |
| 7993815 | Line ends forming Methods of forming line ends and a related memory cell including the line ends are disclosed. In one embodiment, the method includes forming a first device element and a second device element separated from the first device element by a space; and forming a first li... | 08/09/2011 |
| 7993504 | Backside unlayering of MOSFET devices for electrical and physical characterization A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plas... | 08/09/2011 |
| 7960095 | Use of mixed bases to enhance patterned resist profiles on chrome or sensitive substrates Resist compositions having good footing properties even on difficult substrates are obtained by using a combination of base additives including a room temperature solid base, and a liquid low vapor pressure base. The compositions are especially useful on metal subst... | 06/14/2011 |
| 7951708 | Copper interconnect structure with amorphous tantalum iridium diffusion barrier A method of forming a diffusion barrier for use in semiconductor device manufacturing includes depositing, by a physical vapor deposition (PVD) process, an iridium doped, tantalum based barrier layer over a patterned interlevel dielectric (ILD) layer, wherein the ba... | 05/31/2011 |
| 7881891 | Automated dynamic metrology sampling system and method for process control A system and method for optimizing and implementing a metrology sampling plan. A system is provided that includes a system for collecting historical metrology data from a metrology tool; and a reduction analysis system that compares an initial capability calculated ... | 02/01/2011 |
| 7791144 | High performance stress-enhance MOSFET and method of manufacture The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain of the PFET and varying thickness of the PFET and NFET channel. ... | 09/07/2010 |
| 7759702 | Hetero-junction bipolar transistor (HBT) and structure thereof A method of fabricating a hetero-junction bipolar transistor (HBT) is disclosed, where the HBT has a structure incorporating a hetero-junction bipolar structure disposed on a substrate including of silicon crystalline orientation . The hetero-junction bipolar s... | 07/20/2010 |
| 7757233 | Controlling a computer system having a processor including a plurality of cores Controlling a computer system having at least one processor including a plurality of cores includes establishing a core max value that sets a maximum number of the plurality of cores operating at a predetermined time period based on an operating condition, determini... | 07/13/2010 |
| 7739071 | System validation using validation programs depicted using markup language System validation using validation programs for a plurality of root functions depicted using a markup language is disclosed. One embodiment of a method includes establishing a validation program template defining a style of input/output usable by a plurality of root... | 06/15/2010 |
| 7732288 | Method for fabricating a semiconductor structure A method for fabricating a semiconductor structure. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. A semiconductor layer and a ga... | 06/08/2010 |
| 7727825 | Polyconductor line end formation and related mask Methods of forming adjacent polyconductor line ends and a mask therefor are disclosed. In one embodiment, the method includes forming a polyconductor layer over an isolation region; forming a mask over the polyconductor layer, the mask including shapes to create the... | 06/01/2010 |
| 7714452 | Structure and method for producing multiple size interconnections An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises ... | 05/11/2010 |
| 7696025 | Sidewall semiconductor transistors A novel transistor structure and method for fabricating the same. First, a substrate, a semiconductor region, a gate dielectric region, and a gate block are provided. The semiconductor region, the gate dielectric region, and the gate block are on the substrate. The ... | 04/13/2010 |
| 7674324 | Exposures system including chemical and particulate filters containing chemically modified carbon nanotube structures An exposure system for exposing a photoresist layer on a top surface of a wafer to light. The exposure system including: an environment chamber containing a light source, one or more focusing lenses, a mask holder, a slit and a wafer stage, the light source, all ali... | 03/09/2010 |
| 7670901 | Method of fabricating a bottle trench and a bottle trench capacitor A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substr... | 03/02/2010 |
| 7668683 | Numerical test data reporting in an image file and subsequent analysis The present disclosure is directed to numerical test data reporting using an image file and subsequent analysis of the test data. A method for capturing and analyzing test data in accordance with an embodiment includes: capturing multi-bit integer values of test dat... | 02/23/2010 |
| 7660350 | High-speed multi-mode receiver A data receiver is provided which is operable to receive a signal controllably pre-distorted and transmitted by a transmitter, to generate information for adjusting the pre-distortion applied to the signal transmitted by the transmitter, and to transmit the informat... | 02/09/2010 |
| 7659616 | On-chip cooling systems for integrated circuits Structures and methods for forming the same. A semiconductor chip includes a substrate and a transistor. The chip includes N interconnect layers on the substrate, N being a positive integer. The chip includes a cooling pipes system inside the N interconnect layers. ... | 02/09/2010 |
| 7659050 | High resolution silicon-containing resist Non-chemically amplified radiation sensitive resist compositions containing silicon are especially useful for lithographic applications, especially E-beam lithography. More particularly, radiation-sensitive resist compositions comprising a polymer having at least on... | 02/09/2010 |
| 7655967 | DRAM (dynamic random access memory) cells A DRAM cell with a self-aligned gradient P-well and a method for forming the same. The DRAM cell includes (a) a semiconductor substrate; (b) an electrically conducting region including a first portion, a second portion, and a third portion; (c) a first doped semicon... | 02/02/2010 |
| 7651831 | Positive photoresist composition with a polymer including a fluorosulfonamide group and process for its use A positive photoresist composition comprises a radiation sensitive acid generator, and a polymer that includes a first repeating unit derived from a sulfonamide monomer including a fluorosulfonamide functionality, a second repeating unit having a pendant acid-labile... | 01/26/2010 |
| 7648819 | Method and apparatus for cleaning a semiconductor substrate in an immersion lithography system A method and apparatus for reduction and prevention of residue formation and removal of residues formed in an immersion lithography tool. The apparatus including incorporation of a cleaning mechanism within the immersion head of an immersion lithographic system or i... | 01/19/2010 |
| 7645621 | Optical inspection methods Inspection methods. A method includes adhering an optical blocking layer directly onto and in direct mechanical contact with a semiconductor process wafer, the blocking layer being substantially opaque to a range of wavelengths of light; applying at least one layer ... | 01/12/2010 |
| 7638264 | Positive photoresist composition with a polymer including a fluorosulfonamide group and process for its use A positive photoresist composition comprises a radiation sensitive acid generator, and a polymer that includes a first repeating unit derived from a sulfonamide monomer including a fluorosulfonamide functionality, a second repeating unit having a pendant acid-labile... | 12/29/2009 |
| 7632631 | Method of preventing pinhole defects through co-polymerization A method is provided for forming a stable thin film on a substrate. The method includes depositing a co-polymer composition having a first component and a second component onto a substrate to form a stable film having a first thickness. The first component has first... | 12/15/2009 |
| 7624369 | Closed-loop design for manufacturability process A method of designing an integrated circuit is provided in which the design layout is optimized using a process model until the design constraints are satisfied by the image contours simulated by the process model. The process model used in the design phase need not... | 11/24/2009 |
| 7608390 | Top antireflective coating composition containing hydrophobic and acidic groups The present invention discloses a composition suitable for use as a top antireflective coating and barrier layer for immersion lithography. The inventive composition is soluble in aqueous base solutions and insoluble in water. The inventive composition comprises a p... | 10/27/2009 |
| 7607114 | Designer's intent tolerance bands for proximity correction and checking A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the... | 10/20/2009 |
| 7587298 | Diagnostic method for root-cause analysis of FET performance variation A diagnostic method of and computer system for root-cause analysis of performance variations of FETs in integrated circuits and a method and computer system for monitoring a field effect transistor manufacturing process. The diagnostic method includes measuring sour... | 09/08/2009 |
| 7569450 | Semiconductor capacitors in hot (hybrid orientation technology) substrates A semiconductor structure and a method for forming the same. The semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an electrically insulating region on top of the semiconductor substrate. The semiconductor struc... | 08/04/2009 |
| 7566527 | Fused aromatic structures and methods for photolithographic applications A resist composition and a method for forming a patterned feature on a substrate. The composition comprises a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, a... | 07/28/2009 |
| 7560966 | Method of testing connectivity using dual operational mode CML latch A method of testing connectivity through a plurality of dual purpose current mode logic (“CML”) latch circuits connected in a series is provided. Each of the CML latch circuits are operable to latch at least one output signal at a timing in accordance with at le... | 07/14/2009 |
| 7560501 | Encapsulant of epoxy or cyanate ester resin, reactive flexibilizer and thermoplastic An encapsulant composition. The encapsulant composition includes a resin material consisting of epoxy or cyanate ester resins, from about 1.0% by weight to about 5% by weight of the composition of a flexibilizing agent including a flexibilizer containing functional ... | 07/14/2009 |
| 7547608 | Polysilicon hard mask for enhanced alignment signal A method is provided for forming a polysilicon layer on a substrate and aligning an exposure system with an alignment feature of the substrate through the polysilicon layer. In such method, a polysilicon layer is deposited over the substrate having the alignment fea... | 06/16/2009 |
| 7544750 | Top antireflective coating composition with low refractive index at 193nm radiation wavelength Compositions characterized by the presence of an aqueous base-soluble polymer having aromatic moieties and a refractive index value n of less than 1.5 with respect to a radiation wavelength of 193 nm have been found which are especially useful as top antireflective ... | 06/09/2009 |
| 7519130 | Front end interface for data receiver A data receiver is provided which includes a front end interface circuit having an alternating current (AC) transmission receiving mode and a direct current (DC) transmission receiving mode. The front end interface circuit includes an offset compensation circuit ope... | 04/14/2009 |
| 7507631 | Epitaxial filled deep trench structures A method of forming and a structure of an electronic device. The method including: forming a trench in a single-crystal semiconductor substrate; forming a dopant diffusion barrier layer on sidewalls and a bottom of the trench; and epitaxially growing a single-crysta... | 03/24/2009 |
