Bizarre Patents
Mouse device with a built-in printer
A mouse device for use as an input device of a computer is provided that includes a housing in which recording paper is loadable, and a printer unit provided within the housing for printing on the recording paper print information received from the computer.
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| Number | Title | Issue Date |
| 8185938 | Method and system for network single-sign-on using a public key certificate and an associated attribute certificate A methodology is presented for a network single sign-on (SSO) authentication process using digital certificates. A user has access to protected resources, such as legacy applications, that require verification of a user's authentication data prior to providing acces... | 05/22/2012 |
| 8125032 | Modified hybrid orientation technology A semiconductor process and apparatus includes forming first and second metal gate electrodes (151, 161) over a hybrid substrate (17) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the seco... | 02/28/2012 |
| 8122802 | Multi-function power saw A power saw includes a saw assembly attached to a base assembly with an offset support that provides a clear path in line with the saw blade, thereby providing a miter saw, a table saw or a radial arm saw The height of the offset support is adjustable to make dado c... | 02/28/2012 |
| 8122437 | Method and apparatus to trace and correlate data trace and instruction trace for out-of-order processors In a data processing system, a marked bit is used to identify a data access instruction throughout the pipeline to indicate that the instruction meets user-specified criteria (e.g., a meets a data address range of interest). Based on the marked bit, an in-order prog... | 02/21/2012 |
| 8117579 | LSSD compatibility for GSD unified global clock buffers A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD cloc... | 02/14/2012 |
| 8103764 | Method and apparatus for matching trigger pattern A method, system and program are disclosed for accelerating data storage in a cache appliance that transparently monitors NFS and CIFS traffic between clients and NAS subsystems and caches files in a cache memory by using a perfect hashing memory index technique to ... | 01/24/2012 |
| 8077803 | Quarter duty cycle pulse generator for interleaved switching mixer An integrated transmit circuit includes a voltage controlled oscillator (702) for generating an input frequency signal (e.g., VCO) that is provided to a divide by two quadrature generator circuit (706) which generates therefrom in-phase and quadrature ... | 12/13/2011 |
| 8068795 | RF multiband transmitter with balun A multi-band RF transmitter circuit (30) for a wireless communication device combines a plurality of RF transmission blocks into a single transceiver integrated circuit which includes a shared broadband SVGA (32), a shared tunable balun (34), an... | 11/29/2011 |
| 8063624 | High side high voltage switch with over current and over voltage protection A method and apparatus are described for providing a current mirror type high voltage switching circuit (60) having a reference branch (M2, M3, R1) and a tracking branch (M1, M5), where the output peak current is limited by ... | 11/22/2011 |
| 8030173 | Silicon nitride hardstop encapsulation layer for STI region A semiconductor process and apparatus provides an encapsulated shallow trench isolation region by forming a silicon nitride layer (96) to cover a shallow trench isolation region (95), depositing a protective dielectric layer (97, 98) over the si... | 10/04/2011 |
| 8023457 | Feedback reduction for MIMO precoded system by exploiting channel correlation In a closed-loop wireless communication system, a codebook-based precoding feedback compression mechanism is provided to remove redundancy from the precoding feedback that is caused by channel correlation in time and frequency. Redundancy due to temporal correlation... | 09/20/2011 |
| 8018002 | Field effect resistor for ESD protection An electrostatic discharge protection device and methodology are provided for protecting semiconductor devices against electrostatic discharge events by temporarily forming during normal (non-ESD) operation two more inversion layers (112, 113) in a first well... | 09/13/2011 |
| 8017469 | Dual high-k oxides with sige channel A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas ... | 09/13/2011 |
| 8003454 | CMOS process with optimized PMOS and NMOS transistor devices A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS de... | 08/23/2011 |
| 8000735 | Wireless modem architecture for reducing memory components A wireless communications device includes a host processing unit, a modem processing unit, and a memory transport interface. The wireless communications device typically runs a variety of software tasks, some of which require considerably more memory than others. By... | 08/16/2011 |
| 7990937 | Initiation of high speed overlay mode for burst data and real time streaming (audio) applications In a wireless 802.15.4 communication system, a method and system are provided for switching between a predetermined protocol transmission mode and a high-speed transmission mode by including signaling mode information in a data packet (330, 340) to instruct t... | 08/02/2011 |
| 7987239 | Method and system for caching role-specific fragments A method, a system, an apparatus, and a computer program product are presented for a fragment caching methodology. After a message is received at a computing device, a fragment in the message body is cached. Cache ID rules from an origin server accompany a fragment ... | 07/26/2011 |
| 7983235 | High speed overlay mode for burst data and real time streaming (audio) applications In a wireless 802.15.4 communication system (300), a high-speed data frame structure (340) is provided which uses the 802.15.4 SHR structure that is spread modulated to obtain the synchronization benefits of the 802.15.4 protocol, but which uses a modi... | 07/19/2011 |
| 7981730 | Integrated conformal shielding method and process using redistributed chip packaging An integrated conformal electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a plurality of modules (30-33) to a process carrier (1) using a double side adhesive... | 07/19/2011 |
| 7979671 | Dual hash indexing system and methodology A method, system and program are disclosed for accelerating data storage in a cache appliance that transparently monitors NFS and CIFS traffic between clients and NAS subsystems and caches files in a cache memory by using a dual hash technique to rapidly store and/o... | 07/12/2011 |
| 7966219 | System and method for integrated recommendations A recommendation appliance, system and method are provided for generating and deploying additional web page content or functionality (e.g., retail recommendations) to an existing web page server system. For example, the present invention may be embodied as a reverse... | 06/21/2011 |
| 7965773 | Macroblock cache A video processing apparatus and methodology use a combination of a processor and a video decoding hardware block to decode video data by using a reference block cache memory to perform motion compensation decode operations in the video decoding hardware block. To i... | 06/21/2011 |
| 7962770 | Dynamic processor reconfiguration for low power without reducing performance based on workload execution characteristics A method, system and program are provided for dynamically reconfiguring a pipelined processor to operate with reduced power consumption without reducing existing performance. By monitoring or detecting the performance of individual units or stages in the processor a... | 06/14/2011 |
| 7961807 | Reference signaling scheme using compressed feedforward codebooks for multi-user, multiple input, multiple output (MU-MIMO) systems A multi-user multiple input multiple output (MIMO) downlink beamforming system with limited feed forward (200) is provided to enable precoding matrix information to be efficiently provided to a subset of user equipment devices (201.i), where zer... | 06/14/2011 |
| 7955968 | Pseudo hybrid structure for low K interconnect integration A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer (43) of ultra low dielectric constant (ULK) material, depositing a second uncured trench layer (51) of the same ULK ma... | 06/07/2011 |
| 7951695 | Method for reducing plasma discharge damage during processing A semiconductor process and apparatus to provide a way to reduce plasma-induced damage by applying a patterned layer of photoresist (114) which includes resist openings formed (117) over the active circuit areas (13, 14) as well as additional re... | 05/31/2011 |
| 7948902 | Method of generating packets without repetition in verification of a device In the present method for use in verification of a device, a plurality of injection flags are provided, each of which is associated with one of a plurality of packet classes. Each injection flag may be of a first or a second state. Next, a packet is generated. If th... | 05/24/2011 |
| 7947589 | FinFET formation with a thermal oxide spacer hard mask formed from crystalline silicon layer A semiconductor process and apparatus provide a FinFET device by forming a second single crystal semiconductor layer (19) that is isolated from an underlying first single crystal semiconductor layer (17) by a buried insulator layer (18); pattern... | 05/24/2011 |
| 7941591 | Flash DIMM in a standalone cache appliance system and methodology A method, system and program are disclosed for accelerating data storage in a cache appliance cluster that transparently monitors NFS and CIFS traffic between clients and NAS subsystems and caches files in a multi-rank flash DIMM cache memory by pipelining multiple ... | 05/10/2011 |
| 7913079 | Method and system for selective email acceptance via encoded email identifiers A method, system, apparatus, and computer program product are presented for providing a user with the ability to limit the receipt of unwanted email messages. An encoded email identifier is generated by combining the user's local mailbox identifier along with encode... | 03/22/2011 |
| 7900521 | Exposed pad backside pressure sensor package A method and apparatus are described for fabricating an exposed backside pressure sensor (30) which protects interior electrical components (37) formed on a topside surface of a pressure sensor transducer die (31) from corrosive particles using ... | 03/08/2011 |
| 7883953 | Method for transistor fabrication with optimized performance A semiconductor process and apparatus includes forming channel orientation CMOS transistors (24, 34) with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer ... | 02/08/2011 |
| 7879666 | Semiconductor resistor formed in metal gate stack A semiconductor process and apparatus fabricate a metal gate electrode (30) and an integrated semiconductor resistor (32) by forming a metal-based layer (26) and semiconductor layer (28) over a gate dielectric layer (24) and then s... | 02/01/2011 |
| 7877480 | Method and system for peer-to-peer authorization An authorization mechanism within a peer-to-peer network is presented. A central server that operates a centralized data repository search engine within a peer-to-peer network performs authentication and authorization operations with respect to users that access its... | 01/25/2011 |
| 7870337 | Power-aware line intervention for a multiprocessor snoop coherency protocol A snoop coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By provi... | 01/11/2011 |
| 7865631 | Dynamic logical data channel assignment using time-grouped allocations A method, system and program are provided for dynamically allocating DMA channel identifiers to multiple DMA transfer requests that are grouped in time by virtualizing DMA transfer requests into an available DMA channel identifier using a channel bitmap listing of a... | 01/04/2011 |
| 7863876 | Built-in self-calibration (BISC) technique for regulation circuits used in non-volatile memory A reference voltage regulation circuit (143) is provided in which one or more input voltage signals (Vref, Vref′) are selectively coupled to a configurable amplifier (114) which is coupled through a sample and hold circuit (120) to a voltage f... | 01/04/2011 |
| 7851857 | Dual current path LDMOSFET with graded PBL for ultra high voltage smart power applications A dual current path LDMOSFET transistor (40) is provided which includes a substrate (400), a graded buried layer (401), an epitaxial drift region (404) in which a drain region (416) is formed, a first well region (406) in wh... | 12/14/2010 |
| 7843218 | Data latch with structural hold A multiplexed data flip-flop circuit (500) is described in which a multiplexer (510) outputs functional or scan data, a master latch (520) generates a master latch output signal at a hold time under control of a master clock signal, a slave latc... | 11/30/2010 |
| 7820530 | Efficient body contact field effect transistor with reduced body resistance A method for forming a body contacted SOI transistor includes forming a semiconductor layer (103) having a body contact region (120), a body access region (121), and an active region (122). An SOI transistor is formed in the active region... | 10/26/2010 |
