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| Number | Title | Issue Date |
| 8171435 | Integrated circuit structure incorporating an inductor, an associated design method and an associated design system Disclosed are embodiments of a circuit (e.g., an electrostatic discharge (ESD) circuit), a design methodology and a design system. In the circuit, an ESD device is wired to a first metal level (e.g., M1). An inductor is formed in a second metal level (e.g., M5) abov... | 05/01/2012 |
| 8169055 | Chip guard ring including a through-substrate via At least one through-substrate via is formed around the periphery of a semiconductor chip or a semiconductor chiplet included in a semiconductor chip. The at least one through-substrate via may be a single through-substrate via that laterally surrounds the semicondu... | 05/01/2012 |
| 8168474 | Self-dicing chips using through silicon vias Systems and methods simultaneously form first openings and second openings in a substrate. The first openings are formed smaller than the second openings. The method also simultaneously forms a first material in the first openings and the second openings. The first ... | 05/01/2012 |
| 8158453 | Methods of forming silicide strapping in imager transfer gate device A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric... | 04/17/2012 |
| 8157970 | Sputtering target fixture A method and apparatus for sputter deposition. The method including: providing a sputter target having a back surface and an exposed front surface; providing a source of magnetic field lines, the magnetic field lines extending through the sputter target from the bac... | 04/17/2012 |
| 8138607 | Metal fill structures for reducing parasitic capacitance Vertically-staggered-level metal fill structures include inner contiguous metal fill structures and outer contiguous metal fill structures. A dielectric material portion is provided between each contiguous metal fill structure. Vertical extent of each contiguous met... | 03/20/2012 |
| 8131225 | BIAS voltage generation circuit for an SOI radio frequency switch A radio frequency (RF) switch located on a semiconductor-on-insulator (SOI) substrate includes at least one electrically biased region in a bottom semiconductor layer. The RF switch receives an RF signal from a power amplifier and transmits the RF signal to an anten... | 03/06/2012 |
| 8125019 | Electrically programmable resistor An electrically programmable resistor is presented. In one embodiment, a resistor includes a doped body within a substrate; a trapped charge region adjacent to the resistor, the resistance of the resistor controlled by an amount of trapped charge in the trapped char... | 02/28/2012 |
| 8120356 | Measurement methodology and array structure for statistical stress and test of reliabilty structures System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows e... | 02/21/2012 |
| 8120110 | Semiconductor structure including a high performance FET and a high voltage FET on a SOI substrate A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer... | 02/21/2012 |
| 8119456 | Bond pad for wafer and package for CMOS imager An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seat between the bond pad region and an active circuit region, and includes... | 02/21/2012 |
| 8110875 | Structure for charge dissipation during fabrication of integrated circuits and isolation thereof A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures ... | 02/07/2012 |
| 8110853 | Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication A semiconductor structure. The semiconductor structure includes a semiconductor substrate, a first transistor on the semiconductor substrate, and a guard ring on the semiconductor substrate. The semiconductor substrate includes a top substrate surface which defines ... | 02/07/2012 |
| 8105924 | Deep trench based far subcollector reachthrough A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semi... | 01/31/2012 |
| 8105861 | CMOS image sensor with reduced dark current A carbon-containing semiconductor layer is formed on exposed surfaces of a p− doped semiconductor layer abutting sidewalls of a shallow trench. Following formation of a dielectric layer on the carbon-containing semiconductor layer, a surface pinning layer having a... | 01/31/2012 |
| 8093679 | Integrated BEOL thin film resistor In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in th... | 01/10/2012 |
| 8084864 | Electromigration resistant aluminum-based metal interconnect structure A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevat... | 12/27/2011 |
| 8077240 | Methods for enhancing quality of pixel sensor image frames for global shutter imaging The image quality of an image frame from a CMOS image sensor array operated in global shutter mode may be enhanced by dispersing or randomizing the noise introduced by leakage currents from floating drains among the rows of the image frame. Further, the image qualit... | 12/13/2011 |
| 8052799 | By-product collecting processes for cleaning processes An apparatus and a method for operating the same. The method includes providing an apparatus which includes a chamber, wherein the chamber includes first and second inlets, an anode and a cathode structures in the chamber, and a wafer on the cathode structure. A cle... | 11/08/2011 |
| 8044764 | Resistor and design structure having resistor material length with sub-lithographic width A resistor and design structure including at least one resistor material length in a dielectric, each of the least one resistor material length having a sub-lithographic width are disclosed. ... | 10/25/2011 |
| 8044510 | Product and method for integration of deep trench mesh and structures under a bond pad A structure includes a substrate. A trench structure is arranged within the substrate. A film is placed under an interlevel dielectric pad and between portions of the trench structure. ... | 10/25/2011 |
| 8039875 | Structure for pixel sensor cell that collects electrons and holes The present invention relates to a design structure for a pixel sensor cell. The pixel sensor cell approximately doubles the available signal for a given quanta of light. A design structure for a pixel sensor cell having reduced complexity includes an n-type collect... | 10/18/2011 |
| 8039868 | Structure and method for an electrostatic discharge (ESD) silicon controlled rectifier (SCR) structure A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes first and second silicon controlled rectifiers (SCRs) formed in a substrate. Further, the first and the second SCRs each incl... | 10/18/2011 |
| 8039354 | Passive components in the back end of integrated circuits Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed... | 10/18/2011 |
| 8037736 | Non-linearity determination of positioning scanner of measurement tool Determination of non-linearity of a positioning scanner of a measurement tool is disclosed. In one embodiment, a method may include providing a probe of a measurement tool coupled to a positioning scanner; scanning a surface of a first sample with the surface at a f... | 10/18/2011 |
| 8028924 | Device and method for providing an integrated circuit with a unique identification A device and method for providing an integrated circuit with a unique identification. The device is usable on an integrated circuit (IC) for generating an identification (ID) identifying the IC and includes a plurality of identification cells each utilizing one of a... | 10/04/2011 |
| 8026131 | SOI radio frequency switch for reducing high frequency harmonics First doped semiconductor regions having the same type doping as a bottom semiconductor layer and second doped semiconductor regions having an opposite type doping are formed directly underneath a buried insulator layer of a semiconductor-on-insulator (SOI) substrat... | 09/27/2011 |
| 8023021 | High efficiency CMOS image sensor pixel employing dynamic voltage supply A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. T... | 09/20/2011 |
| 8020128 | Scaling of bipolar transistors Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling t... | 09/13/2011 |
| 8018017 | Thermo-mechanical cleavable structure A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure includes an electrically conductive cleavable layer adjacent to a thermo-... | 09/13/2011 |
| 8015538 | Design structure with a deep sub-collector, a reach-through structure and trench isolation The invention relates to noise isolation in semiconductor devices, and a design structure on which a subject circuit resides. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a deep sub-collector loc... | 09/06/2011 |
| 8012814 | Method of forming a high performance fet and a high voltage fet on a SOI substrate A first portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is protected, while a second portion of the top semiconductor layer is removed to expose a buried insulator layer. A first field effect transistor including a gate dielectri... | 09/06/2011 |
| 8009216 | Pixel sensor cell with frame storage capability A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame tr... | 08/30/2011 |
| 8009215 | Pixel sensor cell with frame storage capability A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame tr... | 08/30/2011 |
| 8008696 | Band gap modulated optical sensor A complementary metal-oxide-semiconductor (CMOS) optical sensor structure comprises a pixel containing a charge collection well of a same semiconductor material as a semiconductor layer in a semiconductor substrate and at least another pixel containing another charg... | 08/30/2011 |
| 8008142 | Self-aligned Schottky diode A Schottky barrier diode comprises a doped guard ring having a doping of a second conductivity type in a semiconductor-on-insulator (SOI) substrate. The Schottky barrier diode further comprises a first-conductivity-type-doped semiconductor region having a doping of ... | 08/30/2011 |
| 8006211 | IC chip and design structure including stitched circuitry region boundary identification Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photoli... | 08/23/2011 |
| 8003536 | Electromigration resistant aluminum-based metal interconnect structure A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevat... | 08/23/2011 |
| 8003428 | Method of forming an inverted lens in a semiconductor structure A flat-top convex-bottom lower lens is formed by first applying a positive tone photoresist over a silicon oxide layer and an optional metallic barrier layer thereupon in a back-end-of-line (BEOL) metallization structure. The positive tone photoresist is exposed und... | 08/23/2011 |
| 8003425 | Methods for forming anti-reflection structures for CMOS image sensors Protuberances, having vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode, are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-as... | 08/23/2011 |
