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| Number | Title | Issue Date |
| 8171069 | Streaming digital data filter A method of filtering streaming digital data in real time. The method including: (a) initializing and storing a set of m data elements and an associated set of m pointer data from 1 to m in sequence, m an integer greater than 2; (b) receiving in real time a first or... | 05/01/2012 |
| 8169760 | Signal and power supply integrated ESD protection device An integrated circuit, design structures and methods of forming the integrated circuit which includes a signal pad ESD coupled to an I/O signal pad and a power supply ESD coupled to a source VDD. The signal pad ESD and the power supply ESD are integrated in a single... | 05/01/2012 |
| 8166651 | Through wafer vias with dishing correction methods A method of forming a through wafer via including forming the through wafer via (TWV) into a substrate and through a first dielectric layer over the substrate; planarizing the first dielectric layer using a chemical mechanical polish before forming a second dielectr... | 05/01/2012 |
| 8164397 | Method, structure, and design structure for an impedance-optimized microstrip transmission line for multi-band and ultra-wide band applications A method, structure, and design structure for an impedance-optimized microstrip transmission line for multi-band and ultra-wide band applications. A method includes: forming a plurality of openings in a ground plane associated with a signal line; forming a plurality... | 04/24/2012 |
| 8163612 | Silicon germanium heterostructure barrier varactor Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-cont... | 04/24/2012 |
| 8158988 | Interlevel conductive light shield A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric laye... | 04/17/2012 |
| 8143671 | Lateral trench FETs (field effect transistors) A semiconductor structure and associated method of formation. The semiconductor structure includes a semiconductor substrate, a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor sub... | 03/27/2012 |
| 8143135 | Embedded series deep trench capacitors and methods of manufacture Trench capacitors and methods of manufacturing the trench capacitors are provided. The trench capacitors are very dense series capacitor structures with independent electrode contacts. In the method, a series of capacitors are formed by forming a plurality of insula... | 03/27/2012 |
| 8138857 | Structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance A design structure, structure, and method for providing an on-chip variable delay transmission line with a fixed characteristic impedance. A method of manufacturing a transmission line structure includes forming a signal line of the transmission line structure, form... | 03/20/2012 |
| 8138579 | Structures and methods of forming SiGe and SiGeC buried layer for SOI/SiGe technology Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternatin... | 03/20/2012 |
| 8138546 | Electrostatic discharge protection device and method of fabricating same A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried ox... | 03/20/2012 |
| 8138534 | Anti-reflection structures for CMOS image sensors Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS imag... | 03/20/2012 |
| 8138531 | Structures, design structures and methods of fabricating global shutter pixel sensor cells Pixel sensor cells, method of fabricating pixel sensor cells and design structure for pixel sensor cells. The pixel sensor cells including: a photodiode body in a first region of a semiconductor layer; a floating diffusion node in a second region of the semiconducto... | 03/20/2012 |
| 8130059 | On chip slow-wave structure, method of manufacture and design structure An on-chip slow-wave structure that uses multiple parallel signal paths with grounded capacitance structures, method of manufacturing and design structure thereof is provided. The slow wave structure includes a plurality of conductor signal paths arranged in a subst... | 03/06/2012 |
| 8129844 | Method of forming a metal silicide layer, devices incorporating metal silicide layers and design structures for the devices Electronic devices and design structures of electronic devices containing metal silicide layers. The devices include: a thin silicide layer between two dielectric layers, at least one metal wire abutting a less than whole region of the silicide layer and in electric... | 03/06/2012 |
| 8129772 | Integrated circuit structures with silicon germanium film incorporated as local interconnect and/or contact Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance ... | 03/06/2012 |
| 8125037 | Field effect transistor with channel region edge and center portions having different band structures for suppressed corner leakage Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to t... | 02/28/2012 |
| 8125013 | Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors A semiconductor structure and design structure includes at least a first trench and a second trench having different depths arranged in a substrate, a capacitor arranged in the first trench, and a via arranged in the second trench. ... | 02/28/2012 |
| 8120145 | Structure for a through-silicon-via on-chip passive MMW bandpass filter A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a substrate including a silicon layer. Furthermore, the design structure includes a metal layer on a bottom side of the silic... | 02/21/2012 |
| 8119474 | High performance capacitors in planar back gates CMOS A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first pl... | 02/21/2012 |
| 8114767 | Structure, semiconductor structure and method of manufacturing a semiconductor structure and packaging thereof A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure com... | 02/14/2012 |
| 8111129 | Resistor and design structure having substantially parallel resistor material lengths A resistor and design structure including a pair of substantially parallel resistor material lengths separated by a first dielectric are disclosed. The resistor material lengths have a sub-lithographic dimension and may be spacer shaped. ... | 02/07/2012 |
| 8106728 | Circuit structure and design structure for an optionally switchable on-chip slow wave transmission line band-stop filter and a method of manufacture The present invention generally relates to a circuit structure, design structure and method of manufacturing a circuit, and more specifically to a circuit structure and design structure for an on-chip slow wave transmission line band-stop filter and a method of manu... | 01/31/2012 |
| 8106432 | CMOS imager photodiode with enhanced capacitance A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensit... | 01/31/2012 |
| 8101494 | Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a ca... | 01/24/2012 |
| 8088656 | Fabricating ESD devices using MOSFET and LDMOS A method, including; simultaneously forming a first doped region of an electrostatic discharge protection device and a second doped region of a high-power device by performing a first ion implantation into a semiconductor substrate; and simultaneously forming a thir... | 01/03/2012 |
| 8054597 | Electrostatic discharge structures and methods of manufacture Electrostatic discharge (ESD) structures having a connection to a through wafer via structure and methods of manufacture are provided. The structure includes an electrostatic discharge (ESD) network electrically connected in series to a through wafer via. More speci... | 11/08/2011 |
| 8051120 | Circuit and design structure for a streaming digital data filter A circuit and design structure for a streaming digital data filter embodied in a machine readable medium, the design structure including: a data processing unit and a pointer processing unit, the data processing unit and the pointer unit connected to a control logic... | 11/01/2011 |
| 8043966 | Method for monitoring patterning integrity of etched openings and forming conductive structures with the openings Disclosed are embodiments of a method that both monitors patterning integrity of etched openings (i.e., ensures that lithographically patterned and etched openings are complete) and forms on-chip conductive structures (e.g., contacts, interconnects, fuses, anti-fuse... | 10/25/2011 |
| 8035190 | Semiconductor devices A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The ... | 10/11/2011 |
| 8030202 | Temporary etchable liner for forming air gap An exemplary method lines the sidewalls of a first opening with a sacrificial material and then fills the first opening with a metallic conductor in a manner such that the metallic conductor contacts the substrate. Next, the method selectively removes the sacrificia... | 10/04/2011 |
| 8030167 | Varied impurity profile region formation for varying breakdown voltage of devices Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first op... | 10/04/2011 |
| 8022496 | Semiconductor structure and method of manufacture A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which in... | 09/20/2011 |
| 7994895 | Heat sink for integrated circuit devices A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal c... | 08/09/2011 |
| 7989306 | Method of forming alternating regions of Si and SiGe or SiGeC on a buried oxide layer on a substrate Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternatin... | 08/02/2011 |
| 7979836 | Split-gate DRAM with MuGFET, design structure, and method of manufacture A semiconductor structure for a dynamic random access memory cell, the structure including: a fin of a fin-type field effect transistor (FinFET) device formed over and spaced apart from a conductive region of a substrate; a storage capacitor connected to a first end... | 07/12/2011 |
| 7977200 | Charge breakdown avoidance for MIM elements in SOI base technology and method A semiconductor device including at least one capacitor formed in wiring levels on a silicon-on-insulator (SOI) substrate, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. A method of fabricating a semiconductor structure includ... | 07/12/2011 |
| 7958482 | Stitched circuitry region boundary identification for stitched IC chip layout Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photoli... | 06/07/2011 |
| 7958477 | Structure, failure analysis tool and method of determining white bump location using failure analysis tool A failure analysis tool, a method of using the tool and a design structure for designing a mask for protecting a critical area of wiring failure in a semiconductor chip during packaging is provided. The failure analysis tool includes a computer infrastructure operab... | 06/07/2011 |
| 7943438 | Structure and method for a silicon controlled rectifier (SCR) structure for SOI technology A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated. ... | 05/17/2011 |
