Bizarre Patents
Crispy Chip Sandwich and Process of Producing a Sandwich Product
A food product comprising a multilayer cookie or snack having outer layers formed from a crispy type edible food product such as a potato chip or corn chip, etc. with an intermediate marshmallow layer being in contact with the inner surface of each crispy chip and one or more filler substances.
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| Number | Title | Issue Date |
| 8176280 | Use of test protection instruction in computing environments that support pageable guests Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is prote... | 05/08/2012 |
| 8176279 | Managing use of storage by multiple pageable guests of a computing environment Management of storage used by pageable guests of a computing environment is facilitated. An enhanced suppression-on-protection facility is provided that enables the determination of which level of protection (host or guest) caused a fault condition, in response to a... | 05/08/2012 |
| 8151213 | System, method and program product for tabular data with dynamic visual cells An apparatus, method and program product for providing dynamic visual cells in tabular data. A computer has an application for selecting a range of cells in said tabular data. A routine within the application recognizes a request for a graphical plot for data contai... | 04/03/2012 |
| 8151083 | Dynamic address translation with frame management What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame ... | 04/03/2012 |
| 8150855 | Performing an efficient implicit join of multiple mixed-type records A method, system, method and computer program product for retrieving data. Records are retrieved from a hierarchical database. The records are categorized into a plurality of record types. Each record comprises a unique identifier field. A record map contains zero o... | 04/03/2012 |
| 8145802 | Extended input/output measurement word facility and emulation of that facility An Extended Input/output (I/O) measurement word facility is provided. Provision is made for emulation of the Extended I/O measurement word facility. The facility provides for storing measurement data associated with a single I/O operation in an extended measurement ... | 03/27/2012 |
| 8131945 | Disowning cache entries on aging out of the entry Caching where portions of data are stored in slower main memory and are transferred to faster memory between one or more processors and the main memory. The cache is such that an individual cache system must communicate to other associated cache systems, or check wi... | 03/06/2012 |
| 8131934 | Extract cache attribute facility and instruction therefore A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) ... | 03/06/2012 |
| 8122268 | Reducing power consumption of mirrored RAID subsystems Power consumption reduction of a mirrored RAID storage subsystems is disclosed, wherein data are mirrored to a secondary mirror disk system, the secondary mirror disk system alternates between an operational stage and a power-save stage, wherein data to be mirrored ... | 02/21/2012 |
| 8122224 | Clearing selected storage translation buffer entries bases on table origin address An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region t... | 02/21/2012 |
| 8122195 | Instruction for pre-fetching data and releasing cache lines A prefetch data machine instruction having an M field performs a function on a cache line of data specifying an address of an operand. The operation comprises either prefetching a cache line of data from memory to a cache or reducing the access ownership of store an... | 02/21/2012 |
| 8117614 | Extract CPU time facility An efficient facility for determining resource usage, such as a processor time used by tasks. The determination is performed on behalf of user applications that do not require a call to operating system services. The facility includes an instruction that determines ... | 02/14/2012 |
| 8117417 | Dynamic address translation with change record override What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. A segment table entry obtained from ... | 02/14/2012 |
| 8103860 | Optional function multi-function instruction A method, system and program product for executing a multi-function instruction in a computer system by specifying, via the multi-function instruction, either a capability query or execution of a selected function of one or more optional functions, wherein the selec... | 01/24/2012 |
| 8103851 | Dynamic address translation with translation table entry format control for indentifying format of the translation table entry What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual addr... | 01/24/2012 |
| 8099274 | Facilitating input/output processing of one or more guest processing systems An article of manufacture, method and system are provided for facilitating input/output (I/O) processing of at least one guest processing system. The article of manufacture includes at least one computer-usable medium having computer-readable program code logic to f... | 01/17/2012 |
| 8095773 | Dynamic address translation with translation exception qualifier What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the v... | 01/10/2012 |
| 8090687 | Just-in-time publishing via a publish/subscribe messaging system having message publishing controls A system and program product having at least one subscriber subscribing to topics from one or more data sources. The number of subscriptions for each data source are registered in a table in real time. Upon detecting subscription activity, a matching routine compare... | 01/03/2012 |
| 8086811 | Optimizations of a perform frame management function issued by pageable guests Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations ma... | 12/27/2011 |
| 8086657 | Adder structure with midcycle latch for power reduction A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from... | 12/27/2011 |
| 8082405 | Dynamic address translation with fetch protection In an enhanced dynamic address translation facility a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are used to access a segment table entry containing a format control field and an acces... | 12/20/2011 |
| 8078843 | Facilitating processing in a computing environment using an extended drain instruction An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalle... | 12/13/2011 |
| 8077062 | Pack ASCII zSeries instructions ASCII input data to be packed into memory is obtained. The ASCII input data includes a plurality of blocks of ASCII data. wherein each block of ASCII data includes a plurality of ASCII characters. A block of ASCII data to he packed is selected. The selected block is... | 12/13/2011 |
| 8056074 | System, and computer program product for on demand enablement of dormant computing resources A system and program product for enabling dormant computer hardware resources in a computer system having a set of dormant computer hardware resources. The method includes accepting a customer request to enable a set of dormant hardware resources, and providing comp... | 11/08/2011 |
| 8055960 | Self test apparatus for identifying partially defective memory A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable t... | 11/08/2011 |
| 8055801 | Pulse-per-second attachment for STP A time synchronization apparatus, method and system are provided. In one aspect, the apparatus comprises at least a time of day clock, a first port operable to receive at least first time information using a first time protocol, a second port operable to receive at ... | 11/08/2011 |
| 8041923 | Load page table entry address instruction execution based on an address translation format control field What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be perf... | 10/18/2011 |
| 8041922 | Enhanced dynamic address translation with load real address function What is provided is a load real address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction containing an opcode is obtained indicating that a load real address is to be performed. The instruction further identi... | 10/18/2011 |
| 8037278 | Dynamic address translation with format control What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual addr... | 10/11/2011 |
| 8024741 | Dynamic latch request scaling back function to conditionally place task in suspended state A computer system dynamically scales back latch requests for system resources. Tasks seeking access to system resources each dynamically determine the probability that the task will gain access to the latch relating to a given system resource. Where the task estimat... | 09/20/2011 |
| 8019964 | Dynamic address translation with DAT protection What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of any one of a region first table, a region second table, a region third table, or a segment table are obtained... | 09/13/2011 |
| 8019922 | Interruption facility for adjunct processor queues Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queu... | 09/13/2011 |
| 8015335 | Performing a configuration virtual topology change and instruction therefore In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topol... | 09/06/2011 |
| 8010925 | Method and system for placement of electric circuit components in integrated circuit design The invention relates to a method and a system for placing electric circuits in integrated circuit chip design. Specifically, the invention encompasses performing a global placement step placing the cells into bins on the chip, as well as a detailed placement proces... | 08/30/2011 |
| 8001411 | Generating a local clock domain using dynamic controls A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clo... | 08/16/2011 |
| 8001328 | Method and process for expediting the return of line exclusivity to a given processor through enhanced inter-node communications A method and apparatus in which the observability of cross-invalidates requests within remote nodes is controlled at the time of a partial response generation, when a remote request initially checks/snoops the directory state of the remote node, but before such the ... | 08/16/2011 |
| 8001225 | Server time protocol messages and methods Server time protocol (STP) messages and methods of exchange thereof are provided for facilitating synchronization of processing units of a timing network. The STP messages include exchange time parameters (XTP) commands and responses, and STP control (STC) commands ... | 08/16/2011 |
| 7996585 | Method and system for state tracking and recovery in multiprocessing computing systems Disclosed are a method and system of tracking real time use of I/O control blocks on a processing unit basis, in a multiprocessing system, such that in the case of a processing unit failure, a list accurately and concisely identifies the control blocks that need to ... | 08/09/2011 |
| 7990158 | Measurement arrangement for determining the characteristic line parameters by measuring scattering parameters The present invention relates to a measurement arrangement for determining the characteristic line parameters by measuring the S-parameters as a function of the frequency of transmission lines. A voltage mesh and a ground mesh in a metal layer are connected symmetri... | 08/02/2011 |
| 7987584 | Article extraction / insertion tool and assembly A tool assembly for removing an article from, or inserting an article onto, a printed circuit board which includes a tool housing having a handle portion and an article receiving portion, a plate slidable within the housing, the plate having a handle portion at a fi... | 08/02/2011 |
