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| Number | Title | Issue Date |
| 8180970 | Least recently used (LRU) compartment capture in a cache memory system A two pipe pass method for least recently used (LRU) compartment capture in a multiprocessor system. The method includes receiving a fetch request via a requesting processor and accessing a cache directory based on the received fetch request, performing a first pipe... | 05/15/2012 |
| 8176406 | Hard error detection An error detection system is provided. The system includes a data array that includes one or more data entries. A copy datastore selectively stores a copy of a first single data entry of the data array. An index generator selectively increments an index that referen... | 05/08/2012 |
| 8176301 | Millicode assist instructions for millicode store access exception checking Millicode store access checking instructions are provided via an operand access control register (OACR) including a test modifier indicator, which is communicatively coupled to an instruction unit subsystem, the instruction unit subsystem for fetching and decoding i... | 05/08/2012 |
| 8176222 | Early termination of an I/O operation in an I/O processing system A computer program product, apparatus, and method for handling early termination of an I/O operation at a channel subsystem in an I/O processing system are provided. The computer program product includes a tangible storage medium readable by a processing circuit and... | 05/08/2012 |
| 8165864 | Method, system and computer program product for verifying address generation, interlocks and bypasses Method, system and computer program product for verifying the address generation, address generation interlocks, and address generation bypassing controls in a CPU. An exemplary embodiment includes a verification method in a processor, the method including propagati... | 04/24/2012 |
| 8161091 | Method for performing decimal floating point addition A method for performing a decimal floating point operation including receiving a first operand having a first coefficient and a first exponent into a first register. A second operand having a second coefficient and a second exponent are received into a second regist... | 04/17/2012 |
| 8140951 | Method and system for instruction address parity comparison A method and system for instruction address parity comparison are provided. The method includes calculating an instruction address parity value for an instruction, and distributing the instruction address parity value to one or more functional units in processing ci... | 03/20/2012 |
| 8140834 | System, method and computer program product for providing a programmable quiesce filtering register A system, method and computer program product for providing a programmable quiesce filtering register. The method includes receiving a quiesce interruption request at the processor. The processor is executing in a mode. A filtering zone associated with the mode is i... | 03/20/2012 |
| 8140713 | System and program products for facilitating input/output processing by using transport control words to reduce input/output communications A computer program product, apparatus, and method for facilitating input/output processing of a processing environment are provided. The computer program product is provided for performing a method including: obtaining by an input/output communications adapter of th... | 03/20/2012 |
| 8140607 | Method for providing a decimal multiply algorithm using a double adder A method for performing decimal multiplication including storing a multiplier and a multiplicand in operand registers, the multiplier including one or more digits. A running sum is stored in a shifter and initialized to zero. The method includes performing for each ... | 03/20/2012 |
| 8135978 | Performing a perform timing facility function instruction for sychronizing TOD clocks A system, method and computer program product for performing a Perform Timing Facility (PTFF) instruction for steering a Time of Day (TOD) clock of the computer system for synchronizing the TOD clock with TOD clocks of other computer systems. The computer system com... | 03/13/2012 |
| 8132038 | System and method for calibrating a time of day (TOD) clock in a computing system node provided in a multi-node network A system, method and computer program product for calibrating a Time Of Day (TOD)-clock in a computing system node provided in a multi-node network. The network comprises an infrastructure of computing devices each having a physical clock providing a time base for e... | 03/06/2012 |
| 8131937 | Apparatus and method for improved data persistence within a multi-node system Improved access to retained data useful to a system is accomplished by managing data flow through cache associated with the processor(s) of a multi-node system. A data management facility operable with the processors and memory array directs the flow of data from th... | 03/06/2012 |
| 8131936 | Method and apparatus for implementing a combined data/coherency cache A method and apparatus for implementing a combined data/coherency cache for a shared memory multi-processor. The combined data/coherency cache includes a system cache with a number of entries. The method includes building a system cache directory with a number of en... | 03/06/2012 |
| 8127118 | Microarchitecture, method and computer program product for efficient data gathering from a set of trace arrays An architecture for collecting performance data in a processor, that includes: a trace read control unit and a trace data collect unit, each unit coupled to a plurality of trace array and multiplex units for providing performance data, the coupling accomplished by a... | 02/28/2012 |
| 8117403 | Transactional memory system which employs thread assists using address history tables A computing system uses specialized “Set Associative Transaction Tables” and additional “Summary Transaction Tables” to speed the processing of common transactional memory conflict cases and those which employ assist threads using an Address History Table an... | 02/14/2012 |
| 8117347 | Providing indirect data addressing for a control block at a channel subsystem of an I/O processing system An computer program product, apparatus, and method for facilitating input/output (I/O) processing for an I/O operation at a host computer system configured for communication with a control unit. The computer program product includes a tangible storage medium readabl... | 02/14/2012 |
| 8112174 | Processor, method and computer program product for fast selective invalidation of translation lookaside buffer A processor including a microarchitecture adapted for invalidating mapping of at least one logical address to at least one absolute address, includes: at least one translation lookaside buffer (TLB) and a plurality of copies thereof; logic for independent indexing o... | 02/07/2012 |
| 8108570 | Determining the state of an I/O operation A state of an input/output (I/O) operation in an I/O processing system is determined. A request for performing the I/O operation is received from an I/O operating system at a channel subsystem and forwarded to a control unit controlling an I/O device for executing t... | 01/31/2012 |
| 8095847 | Exception condition handling at a channel subsystem in an I/O processing system A computer program product, apparatus, and method for handling exception condition feedback at a channel subsystem of an I/O processing system using data from a control unit are provided. The computer program product includes a tangible storage medium readable by a ... | 01/10/2012 |
| 8095837 | Method and apparatus for improving random pattern testing of logic structures A test method and apparatus for randomly testing logic structures. The method includes identifying and analyzing a functional behavior of a logic structure to be covered during the random testing, modifying the logic structure such that the logic structure behaves i... | 01/10/2012 |
| 8095750 | Transactional memory system with fast processing of common conflicts A computing system processes memory transactions for parallel processing of multiple threads of execution by support of which an application need not be aware. The computing system transactional memory support provides a Transaction Table in memory and performs fast... | 01/10/2012 |
| 8095741 | Transactional memory computing system with support for chained transactions A computing system processes memory transactions for parallel processing of multiple threads of execution provides execution of multiple atomic instruction groups (AIGs) on multiple systems to support a single large transaction that requires operations on multiple t... | 01/10/2012 |
| 8090933 | Methods computer program products and systems for unifying program event recording for branches and stores in the same dataflow The present invention relates to a method for the unification of PER branch and PER store operations within the same dataflow. The method comprises determining a PER range, the PER range comprising a storage area defined by a designated storage starting area and a d... | 01/03/2012 |
| 8090883 | Method, system and computer program product for enhanced shared store buffer management scheme with limited resources for optimized performance The exemplary embodiment of the present invention provides a storage buffer management scheme for I/O store buffers. Specifically, the storage buffer management system as described within the exemplary embodiment of the present invention is configured to comprise st... | 01/03/2012 |
| 8082481 | Multiple CRC insertion in an output data stream A computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a message to transmit from the channel subsystem to... | 12/20/2011 |
| 8041894 | Method and system for a multi-level virtual/real cache system with synonym resolution Method and system for a multi-level virtual/real cache system with synonym resolution. An exemplary embodiment includes a multi-level cache hierarchy, including a set of L1 caches associated with one or more processor cores and a set of L2 caches, wherein the set of... | 10/18/2011 |
| 8032716 | System, method and computer program product for providing a new quiesce state A system, method and computer program product for providing a new quiesce state. The method includes receiving a quiesce request at a system controller from an initiating processor. The quiesce request is sent to a plurality of processors. Notification is received a... | 10/04/2011 |
| 8032709 | System, method and computer program product for handling shared cache lines in a multi-processor environment A system, method, and computer program product for handling shared cache lines to allow forward progress among processors in a multi-processor environment is provided. A counter and a threshold are provided a processor of the multi-processor environment, such that t... | 10/04/2011 |
| 8028180 | Method and system for power conservation in a hierarchical branch predictor A method and system for power conservation in a hierarchical branch predictor system are provided. The method includes addressing multiple branch predictors, each of the branch predictors having various sizes of hierarchical storage and storing information about pre... | 09/27/2011 |
| 8015362 | Method and system for handling cache coherency for self-modifying code A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amo... | 09/06/2011 |
| 8006039 | Method, system, and computer program product for merging data A method for merging data including receiving a request from an input/output device to merge a data, wherein a merge of the data includes a manipulation of the data, determining if the data exists in a local cache memory that is in local communication with the input... | 08/23/2011 |
| 8001520 | Methodology for generating accessing functions for programmed execution of panel-driven business applications A method of providing access to Business Applications (BA) executed on a data processing system, BAs offer their services interactively controlled by a multitude of BA panels. The individual panels, the sequence of the panels as they are displayed by the BA, and the... | 08/16/2011 |
| 8001298 | Providing extended measurement data in an I/O processing system An article of manufacture, an apparatus, and a method for providing extended measurement word data from a control unit to a channel subsystem of an I/O processing system are disclosed. The article of manufacture includes at least one computer usable medium having co... | 08/16/2011 |
| 7997918 | Actuation device having combined mechanisms to match a desired connector plugging curve and method for actuating a power supply therewith An actuation device includes a frame, a linkage mechanism and a handle mechanism. The handle mechanism includes a handle and a connection link, each having a first end and an opposite second end. The first end of the handle is pivotally connected to the frame. The f... | 08/16/2011 |
| 7996203 | Method, system, and computer program product for out of order instruction address stride prefetch performance verification A method, system, and computer program product are provided for verifying out of order instruction address (IA) stride prefetch performance in a processor design having more than one level of cache hierarchies. Multiple instruction streams are generated and the inst... | 08/09/2011 |
| 7987384 | Method, system, and computer program product for handling errors in a cache without processor core recovery A method for handling errors in a cache memory without processor core recovery includes receiving a fetch request for data from a processor and simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor. The fetche... | 07/26/2011 |
| 7987343 | Processor and method for synchronous load multiple fetching sequence and pipeline stage result tracking to facilitate early address generation interlock bypass A pipelined processor including an architecture for address generation interlocking, the processor including: an instruction grouping unit to detect a read-after-write dependency and to resolve instruction interdependency; an instruction dispatch unit (IDU) includin... | 07/26/2011 |
| 7984341 | Method, system and computer program product involving error thresholds A system for processing errors in a processor comprising, an error counter, a pass counter, and a processing portion operative to determine whether a first error is active, increment an error counter responsive to determining that the first error is active, incremen... | 07/19/2011 |
| 7984276 | Method and system for altering processor execution of a group of instructions An embodiment of the invention is a processor for detecting one or more groups of instructions and initiating a processor action upon detecting one or more groups of instructions. The processor includes an instruction unit for fetching and decoding a group of instru... | 07/19/2011 |
