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...During the Civil War, the Confederacy established its own Patent Office which issued 266 patents, a third of which concerned implements of war.
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| Number | Title | Issue Date |
| 5219713 | Multi-layer photoresist air bridge fabrication method The method of constructing an air bridge on a substrate between spaced apart conductors on the substrate with the bridge spanning the distance between the conductors, by using PMGI to build a bridge pad on the substrate; using PMMA to build a bridge patte... | 06/15/1993 |
| 4833042 | Nonalloyed ohmic contacts for n type gallium arsenide The invention is a layered nonalloyed ohmic contact structure for use on n type gallium arsenide including a layer of germanium or silicon of the order of 10 Å thick evaporated onto the gallium arsenide; a diffusion barrier layer of material 100-200 Å t... | 05/23/1989 |
| 4814735 | Magnetic core multiple tap or windings devices Windings for magnetic core devices are preformed as a flat conducting strip disposed in a helical coil configuration of circular shape, having elongated tabs at selectible angles to the coil from substantially tangential to substantially radial orientatio... | 03/21/1989 |
| 4804972 | Monocoque antenna structure An enclosed terrestrial antenna system of monocoque construction for receiving television signals from satellites in geostationary orbit. The basic antenna comprises two dish-shaped members having substantially identical configurations, each of which is a... | 02/14/1989 |
| 4751434 | Self-illuminated sealed cool light display and method The invention comprises a fluid-tight light box containing a cold cathode light source activated by a high frequency ballast circuit small enough to be contained in the box. At least the box bottom interior is coated with a crinkle or matte finish to caus... | 06/14/1988 |
| 4749662 | Diffused field CMOS-bulk process The present invention is a CMOS process for forming an N-channel device and a P-channel device on a doped substrate wherein an active region surrounded by field for the N-channel device is delineated to comprise a thin layer of oxide, a layer of nitride a... | 06/07/1988 |
| 4707808 | Small size, high speed GaAs data latch The invention provides small size, high speed data latches comprising memory cells that are fabricated according to a Gallium Arsenide (GaAs) process. The memory cells are implemented by a relatively few number of depletion metal semiconductor field effec... | 11/17/1987 |
| 4703205 | Uncompensated and compensated gallium arsenide input receivers A gallium arsenide input receiver and method modify a conventional voltage level shifter circuit at its input to adapt it to operate on the lower gallium arsenide input voltages. A gallium arsenide depletion common gate amplifier FET receives the lower ra... | 10/27/1987 |
| 4697328 | Method of making hardened NMOS sub-micron field effect transistors The invention provides a novel high speed hardened NMOS structure and process for developing the structure. In a first embodiment, the surface of the silicon wafer is preserved intact by building the field oxide above this surface so there is no tra... | 10/06/1987 |
| 4694565 | Method of making hardened CMOS sub-micron field effect transistors The invention provides a novel high speed hardened CMOS structure and process for developing the structure. In a first embodiment, the surface of the silicon wafer is preserved intact by building the field oxide above this surface so there is no tra... | 09/22/1987 |
| 4683399 | Silicon vacuum electron devices A vacuum electron device including a semiconductor device in a hermetically sealed container enclosing a vacuum. The device includes an electron emissive source for emitting electrons into the vacuum, and a collector for collecting electrons emitted from ... | 07/28/1987 |
| 4611387 | Process for producing NPN type lateral transistors The invention provides a unique VLSI dimensioned NPN type transistor and method of making the same, wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide complete... | 09/16/1986 |
| 4593453 | Two-level transistor structures and method utilizing minimal area therefor The invention relates to the process for manufacturing and the structure of stacked transistors on a silicon substrate wherein a polysilicon layer is employed which is recrystallized and delineated to form the gate for one transistor and the source, chann... | 06/10/1986 |
| 4587711 | Process for high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field ... | 05/13/1986 |
| 4584762 | Lateral transistor separated from substrate by intersecting slots filled with substrate oxide for minimal interference therefrom and method for producing same The invention is a transistor or array thereof and method for producing same in VLSI dimensions on a silicon substrate doped P or N type by forming intersecting slots in spaced apart relation across the substrate to define semiarrays of V shaped intermedi... | 04/29/1986 |
| 4580331 | PNP-type lateral transistor with minimal substrate operation interference and method for producing same The invention provides a unique VLSI dimensioned PNP-type transistor and method of making the same wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completel... | 04/08/1986 |
| 4560250 | Explosion-proof and fog-free day and night outside rear view mirror incorporating variable position actuator A housing, which is secured for pivoting or biased in a frame by a manual actuated sheathed cable extending from inside the cab, supports a glass sealed at an angle in front of a mirror and heater which aids in defrosting the front of the glass and provid... | 12/24/1985 |
| 4522682 | Method for producing PNP type lateral transistor separated from substrate by O.D.E. for minimal interference therefrom The invention provides a unique sub-micron dimensioned PNP type transistor and method of making the same, wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide co... | 06/11/1985 |
| 4523300 | Chevron detector expander for magnetic bubble domain system A magnetic bubble domain system including a layer of magnetic material in which magnetic bubble domains can be propagated and a bubble domain guide structure coupled to the layer for defining first and second channels for the movement of domains. The bubb... | 06/11/1985 |
| 4506437 | Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field ... | 03/26/1985 |
| 4506283 | Small area high value resistor with greatly reduced parasitic capacitance The invention provides a unique sub-micron dimensioned resistor and methods of making the same, wherein hundreds of such resistors may be fabricated on a single chip with each comprising an active region surrounded by field oxide completely isolating it f... | 03/19/1985 |
| 4504197 | Pumping unit and reversing valve and method of operating The invention relates to apparatus for and a method of remotely reversing the operation of a power piston in a power cylinder automatically to pump oil, corrosive or wax bearing fluids in response to unidirectional high pressure flow. The flow of high pre... | 03/12/1985 |
| 4497685 | Small area high value resistor with greatly reduced parasitic capacitance The invention provides a unique sub-micron dimensioned resistor and methods of making the same, wherein hundreds of such resistors may be fabricated on a single chip with each comprising an active region surrounded by field oxide completely isolating it f... | 02/05/1985 |
| 4485551 | NPN Type lateral transistor separated from substrate by O.D.E. for minimal interference therefrom and method for producing same The invention provides a unique sub-micron dimensioned NPN type transistor and method of making the same, wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide co... | 12/04/1984 |
| 4477962 | Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices. The use of materials in successive layers having different etch characteristics permits selective oxidation of desir... | 10/23/1984 |
| 4466180 | Method of manufacturing punch through voltage regulator diodes utilizing shaping and selective doping The invention is a punch through voltage regulator having an active region formed on a substrate by any one of four different methods. Each method includes recessing the substrate substantially along the periphery of the regulator active region, selective... | 08/21/1984 |
| 4466178 | Method of making extremely small area PNP lateral transistor by angled implant of deep trenches followed by refilling the same with dielectrics An array of hundreds of devices may be simultaneously processed on a chip to sub-micron dimensions by establishing tiny active regions for each transistor surrounded by field oxide filled moats or slotted regions, wherein the slots are utilized to dope th... | 08/21/1984 |
| 4459937 | High rate resist polymerization apparatus An improvement in the method of forming polymerization resists by directing high energy particles such as electron beams along a path across a vacuum chamber and onto polymerizable molecular species at a substrate surface with sufficient energy to polymer... | 07/17/1984 |
| 4455737 | Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field ... | 06/26/1984 |
| 4437226 | Process for producing NPN type lateral transistor with minimal substrate operation interference The invention provides a unique sub-micron dimensioned NPN type transistor and method of making the same wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide com... | 03/20/1984 |
| 4435899 | Method of producing lateral transistor separated from substrate by intersecting slots filled with substrate oxide The invention is a transistor or array thereof and method for producing same in sub-micron dimensions on a silicon substrate doped P or N type by forming slots in spaced apart relation across the substrate to define semi-arrays of V shaped intermediate re... | 03/13/1984 |
| 4423467 | Connection array for interconnecting hermetic chip carriers to printed circuit boards using plated-up pillars The invention comprises a connection array for establishing a plurality of electrical connections between circuit pads of a support, such as a circuit board, and contacts of an electrical housing, such as a hermetic chip carrier, wherein the contacts comp... | 12/27/1983 |
| 4419808 | Method of producing redundant ROM cells The present invention comprises a unique FET with resistor in its drain lead of undoped polysilicon which may be characterized by high resistance in the absence of the application of a biasing voltage across the FET and the resistor when the FET is conduc... | 12/13/1983 |
| 4419150 | Method of forming lateral bipolar transistors The invention is a sub-micron dielectrically isolated transistor and method of making the same wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by a field oxide region, N+ ... | 12/06/1983 |
| 4415371 | Method of making sub-micron dimensioned NPN lateral transistor An array of hundreds of devices may be simultaneously processed on a chip to sub-micron dimensions by establishing tiny active regions for each transistor surrounded by field oxide filled motes or slotted regions, wherein the slots are utilized to dope th... | 11/15/1983 |
| 4406252 | Inductive heating arrangement for evaporating thin film alloy onto a substrate The invention is a thin film alloy source utilizing a supply of alloy wire selected for deposition onto a substrate. The wire is advanced through an induction heating means at a controlled rate for evaporation onto the substrate. Detection of the meniscus... | 09/27/1983 |
| 4404581 | ROM With redundant ROM cells employing a highly resistive polysilicon film for programming the cells The present invention comprises a unique FET with resistor in its drain lead of undoped polysilicon which may be characterized by high resistance in the absence of the application of a biasing voltage across the FET and the resistor when the FET is conduc... | 09/13/1983 |
| 4400407 | Method for deposition of thin film alloys utilizing electron beam vaporization The invention is an apparatus and method for achieving thin film deposition, of uniform composition, from evaporated alloys. A source of wire alloy, selected for the particular thin film deposition on a substrate, is continuously fed through a region of h... | 08/23/1983 |
| 4399373 | FET Power supply for MOS memories The invention applies a reference voltage to a responsive means for producing a signal of one type in the absence of a semi-conductor at the addressed memory location, and applies a voltage less than the reference voltage to the responsive means for produ... | 08/16/1983 |
| 4396479 | Ion etching process with minimized redeposition The invention is a method of minimizing redeposition of thin film material being removed by ion impact via a patterned resist mask, which invention determines the resist mask etching rates in selected atmospheres and determines the material etching rates ... | 08/02/1983 |
