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| Number | Title | Issue Date |
| 8185679 | Controlling bus access An apparatus that controls access by multiple IP cores to a bus is provided. The apparatus includes a main controller and multiple sub controllers, each of the sub controllers being associated with each IP cores. The main controller switches connection between each ... | 05/22/2012 |
| 8171220 | Cache architecture with distributed state bits Embodiments that that distribute replacement policy bits and operate the bits in cache memories, such as non-uniform cache access (NUCA) caches, are contemplated. An embodiment may comprise a computing device, such as a computer having multiple processors or multipl... | 05/01/2012 |
| 8170424 | Method and apparatus for optical signal power discrimination The present invention provides an optical power level discriminating device and method for discriminating optical power levels. The optical discriminating device includes a splitter for receiving an optical signal having first and second signal states, and splitting... | 05/01/2012 |
| 8169321 | Radio frequency-enabled electromigration fuse Embodiments of the invention provides a method, device, and system for programming an electromigration fuse (eFuse) using a radio frequency (RF) signal. A first aspect of the invention provides a method of testing circuitry on a semiconductor chip, the method compri... | 05/01/2012 |
| 8169026 | Stress-induced CMOS device A semiconductor device including: a silicon dioxide layer; an n-type field effect transistor (NFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer; a p-type field effect transistor (PFET) including at leas... | 05/01/2012 |
| 8166423 | Photomask design verification Solutions for verifying photomask designs are disclosed. In one embodiment, a method of verifying a photomask design includes: simulating an initial semiconductor manufacturing process using a plurality of mask shapes and variation models for the initial semiconduct... | 04/24/2012 |
| 8164190 | Structure of power grid for semiconductor devices and method of making the same An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being c... | 04/24/2012 |
| 8161421 | Calibration and verification structures for use in optical proximity correction A method of training an Optical Proximity Correction (OPC) model comprises symmetrizing a complex design to be a test pattern having orthogonal symmetry. Symmetrizing may comprise establishing a axis of symmetry passing through the design, thereby dividing the desig... | 04/17/2012 |
| 8159814 | Method of operating transistors and structures thereof for improved reliability and lifetime Embodiments of the present invention provide a semiconductor device that includes a transistor device having a first, a second, and a third node; and an interconnect structure having at least one wire and the wire having a first and a second end with the first end o... | 04/17/2012 |
| 8159040 | Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structu... | 04/17/2012 |
| 8158014 | Multi-exposure lithography employing differentially sensitive photoresist layers A stack of a second photoresist having a second photosensitivity and a first photoresist having a first photosensitivity, which is greater than second photosensitivity, is formed on a substrate. A first pattern is formed in the first photoresist by a first exposure ... | 04/17/2012 |
| 8144726 | Structure for out of band signaling enhancement for high speed serial driver A design structure is provided for a microelectronic serial driver. The serial driver is operable to transmit a differential pattern signal during a burst interval and a predetermined common mode voltage level during a second interval between adjacent burst interval... | 03/27/2012 |
| 8140825 | Systems and methods for selectively closing pages in a memory Systems, methods and media for selectively closing pages in a memory in anticipation of a context switch are disclosed. In one embodiment, a table is provided to keep track of open pages for different processes. The table comprises rows corresponding to banks of mem... | 03/20/2012 |
| 8140767 | Cache management through delayed writeback The illustrative embodiments provide a method, apparatus, and computer program product for managing a number of cache lines in a cache. In one illustrative embodiment, it is determined whether activity on a memory bus in communication with the cache exceeds a thresh... | 03/20/2012 |
| 8140758 | Data reorganization in non-uniform cache access caches Embodiments that dynamically reorganize data of cache lines in non-uniform cache access (NUCA) caches are contemplated. Various embodiments comprise a computing device, having one or more processors coupled with one or more NUCA cache elements. The NUCA cache elemen... | 03/20/2012 |
| 8138053 | Method of forming source and drain of field-effect-transistor and structure thereof Embodiments of the invention provide a method of forming a field-effect-transistor (FET). The method includes implanting one or more n-type dopants to create one or more implanted regions with at least a portion of the implanted regions being designated as regions f... | 03/20/2012 |
| 8138041 | In-situ silicon cap for metal gate electrode Structure and method of improving the performance of metal gate devices by depositing an in-situ silicon (Si) cap are disclosed. A wafer including a substrate and a dielectric layer is heated through a degas process, and then cooled to approximately room temperature... | 03/20/2012 |
| 8131953 | Tracking store ordering hazards in an out-of-order store queue A method and system for processing data. In one embodiment, the method includes receiving a first store and receiving a second store subsequent to the first store. The method also includes generating a pointer that points to the last store that needs to retire befor... | 03/06/2012 |
| 8130650 | Retro flow control for arriving traffic in computer networks The decision within a packet processing device to transmit a newly arriving packet into a queue to await further processing or to discard the same packet is made by a flow control method and system. The flow control is updated with a constant period determined by st... | 03/06/2012 |
| 8128749 | Fabrication of SOI with gettering layer An SOI substrate has a gettering layer of silicon-germanium (SiGe) with 5-10% Ge, and a thickness of approximately 50-1000 nm. Carbon (C) may be added to SiGe to stabilize the dislocation network. The SOI substrate may be a SIMOX SOI substrate, or a bonded SOI subst... | 03/06/2012 |
| 8126913 | Method to identify exact, non-exact and further non-exact matches to part numbers in an enterprise database A method of searching for customer part numbers stored in an enterprise database includes creating a set of discrete search strings from a set of supplier part numbers by which a search of the customer part numbers is performed and identifying any exact, non-exact a... | 02/28/2012 |
| 8124525 | Method of forming self-aligned local interconnect and structure formed thereby Embodiments of the present invention provide a method of forming local interconnect for semiconductor devices. The method includes depositing a blanket layer of conductive material over one or more semiconductor devices; creating a pattern of local interconnect cove... | 02/28/2012 |
| 8112604 | Tracking load store ordering hazards A method and system for processing data. In one embodiment, the method includes receiving a plurality of stores into a store queue, where each store is a result from a processor, and where the plurality of stores are destined for at least one memory address. The met... | 02/07/2012 |
| 8112547 | Efficiently hashing packet keys into a firewall connection table A method for increasing the capacity of a connection table in a firewall accelerator by means of mapping packets in one session with some common security actions into one table entry. For each of five Network Address Translation (NAT) configurations, a hash function... | 02/07/2012 |
| 8108804 | Short path customized mask correction Embodiments of the present invention provide a method of performing photo-mask correction. The method includes identifying a hot-spot in a photo-mask that violates one or more predefined rules; creating a window area in the photo-mask that surrounds the hot spot; ca... | 01/31/2012 |
| 8106515 | Local metallization and use thereof in semiconductor devices An embodiment of the invention provides a method of creating local metallization in a semiconductor structure, and the use of local metallization so created in semiconductor structures. In one respect, the method includes forming an insulating layer on top of a semi... | 01/31/2012 |
| 8105887 | Inducing stress in CMOS device A first aspect of the invention provides a method of forming a semiconductor device, the method comprising: providing a complimentary metal oxide semiconductor (CMOS) device including: a silicon substrate layer; a silicon dioxide layer thereover; and an n-type field... | 01/31/2012 |
| 8099684 | Methodology of placing printing assist feature for random mask layout Embodiments of the present invention provide a method of placing printing assist features in a mask layout. The method includes providing a design layout having one or more designed features; generating a set of parameters, the set of parameters being associated wit... | 01/17/2012 |
| 8085789 | Algorithm and system for selecting acknowledgments from an array of collapsed VOQ's A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism is disclosed. An egress location for an ingress port is selected based on degrees of freedom for the selection mechani... | 12/27/2011 |
| 8084788 | Method of forming source and drain of a field-effect-transistor and structure thereof A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication pro... | 12/27/2011 |
| 8084346 | Replacement metal gate method A method includes forming a dummy gate in a dielectric layer on a substrate, the dummy gate including a sacrificial oxide layer and a dummy gate body over the sacrificial oxide layer; removing the dummy gate body resulting in a gate opening with the sacrificial oxid... | 12/27/2011 |
| 8084311 | Method of forming replacement metal gate with borderless contact and structure thereof Embodiments of the present invention provide a method of forming borderless contact for transistor in a replacement metal gate process. The method includes forming a gate on top of a substrate and forming spacers adjacent to sidewalls of the gate; lowering height of... | 12/27/2011 |
| 8080451 | Fabricating semiconductor structures Solutions for fabricating a semiconductor structure. One embodiment includes a method for fabricating a semiconductor structure, the method including: forming a first dielectric structure on a substrate, the first dielectric structure including silicon nitride (Si | 12/20/2011 |
| 8059884 | Method and system for obtaining bounds on process parameters for OPC-verification Embodiments of the present invention provide a method of performing printability verification of a mask layout. The method includes creating one or more tight clusters; computing a set of process parameters associated with a point on said mask; comparing said set of... | 11/15/2011 |
| 8053838 | Structures, fabrication methods, design structures for strained fin field effect transistors (FinFets) A semiconductor structure, a fabrication method, and a design structure for a FinFet. The FinFet includes a dielectric layer, a central semiconductor fin region on the dielectric layer, a first semiconductor seed region on the dielectric layer, and a first strain cr... | 11/08/2011 |
| 8053037 | Device and method for patterning structures on a substrate A device for patterning structures on a substrate includes an imaging device having a scanning tip, a light emitting device, and a space around the scanning tip. The space comprises a vapor of a material which is suitable for Chemical Vapor Deposition onto the subst... | 11/08/2011 |
| 8034533 | Fluorine-free heteroaromatic photoacid generators and photoresist compositions containing the same Fluorine-free photoacid generators and photoresist compositions containing fluorine-free photoacid generators are enabled as alternatives to PFOS/PFAS photoacid generator-containing photoresists. The photoacid generators are characterized by the presence of a fluori... | 10/11/2011 |
| 8030154 | Method for forming a protection layer over metal semiconductor contact and structure formed thereon In one embodiment, a method of forming a semiconductor device is provided that includes providing a gate structure on a semiconductor substrate. Sidewall spacers may be formed adjacent to the gate structure. A metal semiconductor alloy may be formed on the upper sur... | 10/04/2011 |
| 8027416 | Structure for data communications systems A machine-readable medium thereupon stored a design structure; the design structure includes a receiver for a data communications system. The receiver includes a data path for receiving a data signal from a data channel, the data path comprising an automatic gain co... | 09/27/2011 |
| 8027415 | Data communications systems A receiver for a data communications system comprises: a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of... | 09/27/2011 |
