Quotables
"To place a man in a multi-stage rocket and project him into the controlling gravitational field of the moon where the passengers can make scientific observations, perhaps land alive, and then return to earth--all that constitutes a wild dream worthy of Jules Verne. I am bold enough to say that such a man-made voyage will never occur regardless of all future advances."
Lee deForest, American radio pioneer ; 1957
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| Number | Title | Issue Date |
| 8174294 | Configurable buffer circuits and methods A buffer circuit includes a current source circuit, first and second switch circuits that are coupled to the current source circuit, a first resistor coupled to the first switch circuit, a second resistor coupled to the second switch circuit, and a third switch circ... | 05/08/2012 |
| 8166376 | Techniques for correcting errors and erasures using a single-shot generalized minimum distance key equation solver A system corrects errors in a codeword. The system includes a channel that sorts reliability numbers of symbols in the codeword to create an ordered list of candidate erasure locations. The system also includes a generalized minimum distance decoder that iteratively... | 04/24/2012 |
| 8159277 | Techniques for providing multiple delay paths in a delay circuit A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuit... | 04/17/2012 |
| 8154328 | Techniques for measuring phases of periodic signals A phase detector circuit generates a phase comparison signal based on a phase difference between first and second periodic signals during a test mode. Phases of the first and the second periodic signals do not change in response to variations in a signal generated b... | 04/10/2012 |
| 8149038 | Techniques for phase adjustment A dynamic phase alignment circuit includes a phase generator circuit having delay-locked loop circuits that generate periodic output signals. Each of the delay-locked loop circuits generates one of the periodic output signals in response to at least two periodic inp... | 04/03/2012 |
| 8138787 | Apparatus and method for input/output module that optimizes frequency performance in a circuit A circuit can include a module having signal pads that are configurable to route signals between the circuit and at least one external device. The module can also have unused pads that are interleaved between the signal pads. A circuit can include a module having si... | 03/20/2012 |
| 8132039 | Techniques for generating clock signals using counters The circuit, typically a delay-locked loop, comprises a phase detector, a first counter, a second counter, and a comparator. The phase detector compares a phase of a first clock signal with a phase of a second clock signal. The first counter generates first count si... | 03/06/2012 |
| 8130016 | Techniques for providing reduced duty cycle distortion A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuit... | 03/06/2012 |
| 8120407 | Techniques for varying phase shifts in periodic signals A circuit includes a phase detection circuit and a phase change circuit. The phase detection circuit compares a phase of a first periodic signal to an input signal to generate a gain signal. The phase change circuit provides phase shifts to the first periodic signal... | 02/21/2012 |
| 8060694 | Techniques for storing system images in slices on data storage devices A data storage device has a data storage medium. A data storage capacity of the data storage device is divided into slices. Each slice has a set of sectors. Data storage device firmware is configured to store copies of a system image in the slices on the data storag... | 11/15/2011 |
| 8037394 | Techniques for generating bit reliability information in a post-processor using an error correction constraint Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfyi... | 10/11/2011 |
| 8037393 | Techniques for generating bit reliability information in the post processor A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post process... | 10/11/2011 |
| 8037377 | Techniques for performing built-in self-test of receiver channel having a serializer A circuit includes a receiver channel and a built-in self-test circuit. The receiver channel has a serializer and a deserializer. The built-in self-test circuit generates test signals that are transmitted in parallel to the serializer during a test of the receiver c... | 10/11/2011 |
| 8035453 | Techniques relating to oscillators An oscillator circuit includes differential variable delay circuits coupled together to form a ring oscillator. Each of the differential variable delay circuits has first and second inputs and first, second, third, and fourth transistors. A constant supply voltage i... | 10/11/2011 |
| 8032689 | Techniques for data storage device virtualization A data storage device comprises virtual storage devices that are each assigned to a subset of data sectors in a non-volatile memory of the data storage device. The data storage device receives configuration metadata for configuring each of the virtual storage device... | 10/04/2011 |
| 8030964 | Techniques for level shifting signals A level shifter circuit includes an input circuit, an inverter, a pull-up circuit, and a pull-down circuit. The input circuit generates a pull-up signal in response to an input signal using charge from a supply voltage. The inverter inverts the input signal to gener... | 10/04/2011 |
| 8019935 | Random number generation for a host system using a hard disk drive A hard disk drive is provided for enhancing random number generation. In particular embodiments, the hard disk drive includes a storage subsystem and a controller. The controller generates a random number based on information associated with the storage subsystem. T... | 09/13/2011 |
| 8010742 | Using idle mode prediction to improve storage system performance Techniques for optimizing hard disk drive performance. According to one embodiment, a storage system includes a storage unit that stores data and a controller. The controller receives an idle mode indication and performs at least one operation based on the idle mode... | 08/30/2011 |
| 8004308 | Techniques for providing calibrated on-chip termination impedance Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. Th... | 08/23/2011 |
| 7999568 | Techniques for serially transmitting on-chip termination control signals Techniques are provided for controlling on-chip termination (OCT) impedance using OCT calibration blocks that serially transmit OCT control signals to input/output (IO) blocks. The OCT control signals are serially transmitted through a shared conductor. An OCT calib... | 08/16/2011 |
| 7994837 | Techniques for phase interpolation A phase interpolator circuit can include first and second transistors coupled to form a differential pair, first and second load circuits, a first switch circuit coupled between the first transistor and the first load circuit, a second switch circuit coupled between... | 08/09/2011 |
| 7994821 | Level shifter circuits and methods A level shifter circuit includes first and second transistors coupled in series and third and fourth transistors coupled in series. The fourth transistor is coupled to a first node between the first and the second transistors. The level shifter circuit also includes... | 08/09/2011 |
| 7994807 | Built-in test circuit for testing AC transfer characteristic of high-speed analog circuit An analog device under test circuit and a built-in test circuit for testing an AC transfer characteristic of the analog device under test are fabricated on an integrated circuit. The built-in test circuit includes an amplitude detector that detects the amplitude of ... | 08/09/2011 |
| 7984344 | Techniques for testing memory circuits An integrated circuit includes a memory circuit, a read address register coupled to a read address port of the memory circuit, a write address register coupled to a write address port of the memory circuit, and a multiplexer configurable to transmit a read address b... | 07/19/2011 |
| 7977984 | High-speed charge pump circuits A charge pump circuit includes at least one switching transistor and a level-shifter. The level-shifter has a cross-coupled pair of transistors. The level-shifter shifts a voltage of a first input signal to generate a level-shifted signal. The level-shifted signal c... | 07/12/2011 |
| 7974037 | Techniques for providing DC-free detection of DC equalization target A data storage device includes a first filter that generates a short DC equalization target in response to a read back signal generated from magnetic patterns that are recorded on a storage medium using perpendicular recording. The data storage device also includes ... | 07/05/2011 |
| 7973553 | Techniques for on-chip termination A circuit includes first transistors and a comparator. The comparator compares a reference signal and a signal that is based on conductive states of the first transistors. A control circuit generates first control signals based on an output signal of the comparator.... | 07/05/2011 |
| 7971241 | Techniques for providing verifiable security in storage devices A verifiable security mode is provided for securing data on a storage device, such as a hard disk drive. When the verifiable security mode is enabled, only authenticated accesses to data stored on the storage device are permitted after entering a password. An end us... | 06/28/2011 |
| 7965465 | Techniques for storing shingle blocks in a cache memory using a data storage device A data storage apparatus includes a data storage medium, a write element, a non-volatile cache memory circuit, and a controller circuit. The controller circuit is configured to record data on the data storage medium in groups of overlapping tracks using the write el... | 06/21/2011 |
| 7957847 | Voltage regulating systems responsive to feed-forward information from deterministic loads Voltage regulating systems are provided that adjust their output control signals in response to feed-forward information that is indicative of deterministic changes in the load current. A feed-forward circuit provides a feed-forward signal in response to an input si... | 06/07/2011 |
| 7956696 | Techniques for generating fractional clock signals A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock sign... | 06/07/2011 |
| 7944248 | Techniques for measuring voltages in a circuit A circuit can include a comparator, a resistor divider, a control circuit, and a multiplexer. The comparator compares an internal supply voltage of the circuit to a selected reference voltage. The resistor divider generates reference voltages. The control circuit re... | 05/17/2011 |
| 7940098 | Fractional delay-locked loops A phase-locked loop includes a phase-to-digital converter that receives a first periodic input signal at a first input and a first feedback signal at a second input. The phase-to-digital converter generates digital signals. A digitally controlled oscillator includes... | 05/10/2011 |
| 7915941 | Phase interpolator circuits and methods A phase interpolator circuit includes first and second low pass filter circuits and a multiplier circuit. The first low pass filter circuit increases a common mode voltage of a clock signal to generate a first varying signal. The second low pass filter circuit incre... | 03/29/2011 |
| 7911240 | Clock switch-over circuits and methods Clock switch-over circuits and methods provide clock signals to clock routing networks. According to one embodiment, a multiplexer selects between a first clock signal and a second clock signal in response to a switch select signal received from a control circuit. A... | 03/22/2011 |
| 7893739 | Techniques for providing multiple delay paths in a delay circuit A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuit... | 02/22/2011 |
| 7886115 | Techniques for implementing virtual storage devices Some embodiments include a storage device with a storage medium having a memory capacity. The storage device also includes virtual storage device firmware that is configured to directly respond to commands from a guest operating system in a virtual machine for acces... | 02/08/2011 |
| 7884644 | Techniques for adjusting level shifted signals A level shifter circuit includes first and second transistors that receive a first input signal at control inputs. A level shifted output signal is generated by the first and the second transistors. Third and fourth transistors receive a second input signal at contr... | 02/08/2011 |
| 7884638 | Techniques for providing calibrated on-chip termination impedance An on-chip termination (OCT) calibration circuit includes one or more transistors coupled between a first terminal and a supply voltage, one or more transistors coupled between the first terminal and a low voltage, and a feedback loop circuit. The feedback loop circ... | 02/08/2011 |
| 7869152 | Techniques for identifying servo sectors in storage devices Techniques are provided for identifying the servo sectors in a track on a data storage device. A data storage device identifies the servo sectors in a track by reading distributed index bits from multiple servo sectors in a track. The data storage device analyzes on... | 01/11/2011 |
