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| Number | Title | Issue Date |
| 5379255 | Three dimensional famos memory devices and methods of fabricating Memory cell transistors are provided in which pillar structures or column structures (12, 12a, 14, and 14a) are formed at the face of a semiconductor substrate (10). Floating gates (46) and control gates (52) are formed adjacent to the pillar structures o... | 01/03/1995 |
| 5365486 | Method and circuitry for refreshing a flash electrically erasable, programmable read only memory A method and apparatus for flash EEPROM refresh is provided in which the control gate of a particular memory cell is read at an elevated control gate voltage (42). It is next determined whether the cell has been programmed (44). If the cell has been progr... | 11/15/1994 |
| 5311480 | Method and apparatus for EEPROM negative voltage wordline decoding A method and apparatus for negative wordline decoding in a flash EEPROM (10) is provided. In particular, a predecoder (26) generates a predecoding signal based on address and invert inputs. The predecoding signal is used to select wordlines in both positi... | 05/10/1994 |
