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| Number | Title | Issue Date |
| 6689678 | Process for fabricating ball grid array package for enhanced stress tolerance The thermomechanical stress sensitivity of ball grid array (BGA) solder connections is significantly reduced, when the solder connections solidify in column-like contours after the reflow process--a result achieved by using the solder material in tapered ... | 02/10/2004 |
| 6688453 | Railing for a boat conveyor system A conveyor system (30) comprises: a boat (20), a feed belt (36), a feed pulley (38), and improved railings (34). The boat (20) is adapted to carry a component or components, such as semiconductor chips (32), therein. The feed belt (36) is driven by the fe... | 02/10/2004 |
| 6685073 | Method and apparatus for stretching and processing saw film tape after breaking a partially sawn wafer A method and apparatus for separating a wafer into wafer portions comprising a larger wafer flex-frame (50) supported on a support base (40) and a smaller flex-frame (60) positioned within the support base (40). A wafer film transfer cylinder (30) encompa... | 02/03/2004 |
| 6602726 | Bond surface conditioning system for improved bondability Thick film bond surfaces (8) on a support structure (10), such as a ceramic substrate or an IC package substrate, tend to deform during processing. A personality kit (16) having raised bosses (24) engages with and compresses the bond surfaces, resulting i... | 08/05/2003 |
| 6597610 | System and method for providing stability for a low power static random access memory cell A system for providing stability for a low power static random access memory (SRAM) cell (10) is provided that includes a wordline (14), a driver (34) and a mode selector (36). The wordline (14) is coupled to the SRAM cell (10). The wordline (14) is opera... | 07/22/2003 |
| 6589865 | Low pressure, low temperature, semiconductor gap filling process A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature... | 07/08/2003 |
| 6584536 | Bus transaction accelerator for multi-clock systems A bus transaction accelerator, incorporating an innovative control register and status register circuit. The innovative accelerator allows systems with different clocks to handshake in the background, thereby reducing bus idle time.... | 06/24/2003 |
| 6583500 | Thin tin preplated semiconductor leadframes A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering the base metal and a plated layer of pure tin, only | 06/24/2003 |
| 6572461 | Method for producing wafer notches with rounded corners and a tool therefor A semiconductor wafer for use in the fabrication of semiconductor devices which includes a circular wafer (13) of semiconductor material having a perimeter and a notch (11) having a wall disposed in the wafer and extending to the perimeter which includes ... | 06/03/2003 |
| 6570242 | Bipolar transistor with high breakdown voltage collector A transistor that includes a doped buried region 320 within a semiconductor body 300, 340. The doped buried region includes a portion having a first thickness 348 and a second thickness, the first thickness being less than the second thickness. In one emb... | 05/27/2003 |
| 6569733 | Gate device with raised channel and method A method of forming a gate device which includes an elongated projection on a substrate. The elongated projection protrudes from a surrounding area of the substrate and includes an access channel for the gate device. A first terminal and a second terminal... | 05/27/2003 |
| 6559523 | Device for attaching a semiconductor chip to a chip carrier In a device for attaching a semiconductor chip (10) to a chip carrier (12), thereby producing an electrically conducting connection between contact areas (22, 24) arranged on a surface of the semiconductor chip (10) and contact areas (26, 28) on the chip ... | 05/06/2003 |
| 6552430 | Ball grid array substrate with improved traces formed from copper based metal A micro-BGA style package for semiconductor device comprises a semiconductor chip and a package substrate. The semiconductor chip includes a plurality of conductive pads. A plurality of transistor circuits are formed upon the semiconductor chip. The packa... | 04/22/2003 |
| 6548359 | Asymmetrical devices for short gate length performance with disposable sidewall An asymmetrical channel implant from source to drain improves short channel characteristics. The implant provides a relatively high VT net dopant adjacent to the source region and a relatively low VT net dopant in the remainder of th... | 04/15/2003 |
| 6534337 | Lead frame type plastic ball grid array package with pre-assembled ball type contacts A method of making a ball grid array package wherein there is provided a partially fabricated package including a semiconductor die, leads and balls secured to predetermined ones of the leads. The leads and balls are concurrently coated with palladium. Th... | 03/18/2003 |
| 6528873 | Ball grid assembly with solder columns A method of making a ball grid assembly and the assembly wherein a mask (1) is provided which is not wettable by solder and through which a pattern of parallel holes (3) is provided extending to at least one of a pair of opposing surfaces. A magnet (5), p... | 03/04/2003 |
| 6525410 | Integrated circuit wireless tagging A semiconductor device comprising an integrated circuit and an information unit, said unit being electrically separate from said integrated circuit; an integrated antenna electrically connected with said unit; and an electronic data bank integral with sai... | 02/25/2003 |
| 6521479 | Repackaging semiconductor IC devices for failure analysis The present invention provides a system and method for preparing semiconductor integrated circuits ("ICs"), particularly ball grid arrays ("BGAs"), quad flat packs ("QFPs") and dual in line packages ("DIPs") for failure analysis ("FA") using a variety of ... | 02/18/2003 |
| 6513085 | Link/transaction layer controller with integral microcontroller emulation An IEEE 1394 serial bus (58) is interfaced utilizing a physical layer (54) to extract the data and a link/transaction layer controller (200) to interface the data from the physical layer (54) to a host system. The host system consists of a peripheral devi... | 01/28/2003 |
| 6512272 | Increased gate to body coupling and application to dram and dynamic circuits An FET and DRAM using a plurality of such FETs wherein each transistor has a body region of a first conductivity type including a relatively high VT region and relatively low VT region, the high VT region disposed contiguo... | 01/28/2003 |
| 6489673 | Digital signal processor/known good die packaging using rerouted existing package for test and burn-in carriers A package for a semiconductor die having a header with a cavity. The cavity includes a floor, sidewalls and a plurality of vertically spaced apart rows along the cavity sidewalls, each row including a plurality of spaced apart bond fingers. An electricall... | 12/03/2002 |
| 6486525 | Deep trench isolation for reducing soft errors in integrated circuits An integrated circuit having improved soft error protection and a method improving the soft error protection of an integrated circuit are disclosed. The integrated circuit comprises a substrate 72, a transistor formed in the substrate 72, a first region 7... | 11/26/2002 |
| 6477312 | Instant replay system A short segment recording and replay system which includes a receiver for receiving and displaying audiovisual information and an endless memory for storage of continuous short segments of the audiovisual information concurrent with display thereof by the... | 11/05/2002 |
| 6476470 | Integrated circuit packaging A method of making semiconductor package and the package comprising the steps of providing a base having a plurality of cavities therein, forming a plurality of sets of spaced apart first apertures extending entirely through the base, each of the sets of ... | 11/05/2002 |
| 6468856 | High charge storage density integrated circuit capacitor An integrated circuit capacitor comprising a high permittivity dielectric and a method of forming the same are disclosed herein. In one embodiment, this capacitor may be used as a DRAM storage cell. For example, a DRAM storage node electrode 22 may be for... | 10/22/2002 |
| 6468837 | Reduced surface field device having an extended field plate and method for forming the same A semiconductor device (10) comprises a reduced surface field (RESURF) implant (14). A field oxide layer (20), having a length, is formed over the RESURF implant (14). A field plate (12) extends from a near-side of the field oxide layer (20) and over at l... | 10/22/2002 |
| 6450397 | Method of making ball grid array columns A method of fabricating solder columns. The method includes the step of providing a substrate having predesignated locations thereon for fabrication of solder columns. An extrusion mold is provided which has apertures extending therethrough and a pair of ... | 09/17/2002 |
| 6443743 | Method for reducing via resistance in small high aspect ratio holes filled using aluminum extrusion A method of forming an electrical interconnect through a via to electrically couple two electrically conductive layers and the device. There are provided a pair of electrically conductive layers and an electrically insulating layer between the pair of ele... | 09/03/2002 |
| 6437007 | Aerogel thin film formation from multi-solvent systems This invention pertains generally to precursors and deposition methods suited to aerogel thin film fabrication. An aerogel precursor sol which contains an oligomerized metal alkoxide (such as TEOS), a high vapor pressure solvent (such as ethanol) and a lo... | 08/20/2002 |
| 6436801 | Hafnium nitride gate dielectric A field effect semiconductor device comprising a high permittivity hafnium (or hafnium-zirconium) nitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel re... | 08/20/2002 |
| 6432317 | Method to produce masking This is a method for masking a structure 12 for patterning micron and submicron features, the method comprises: forming at least one monolayer 32 of adsorbed molecules on the structure; prenucleating portions 46,48 of the adsorbed layer by exposing the po... | 08/13/2002 |
| 6424016 | SOI DRAM having P-doped polysilicon gate for a memory pass transistor An integrated circuit including a DRAM is disclosed, wherein the DRAM includes a memory array including a plurality of pass gate transistors and a plurality of memory elements. The pass gate transistors include a gate material selected to provide a substa... | 07/23/2002 |
| 6420782 | Vertical ball grid array integrated circuit package An integrated circuit package (30, 32) for vertical attachment as part of a high density module (200) comprising a carrier (70) having an opening (86), routing strips (82), conduits (84) and side surface terminals (100), the side surface terminals (100) d... | 07/16/2002 |
| 6420729 | Process to produce ultrathin crystalline silicon nitride on Si (111) for advanced gate dielectrics A method of making a semiconductor device and the device. The device, according to a first embodiment, is fabricated by providing a silicon (111) surface, forming on the surface a dielectric layer of crystalline silicon nitride and forming an electrode la... | 07/16/2002 |
| 6415235 | Fixed optic sensor system and distributed sensor network A sensor control and data analysis system (100) for detecting and analyzing various (bio)chemical properties of a given sample substance (107) using an integrated SPR sensor (50) or other miniaturized sensor configuration. In one embodiment, raw sensor da... | 07/02/2002 |
| 6414533 | Over-voltage tolerant, active pull-up clamp circuit for a CMOS crossbar switch A CMOS bus switch (20) having undershoot protection circuitry (22) to help prevent data corruption when the switch is open and the buses (A,B) are isolated from one another. A bias generator (30) sets a voltage (Bias) referenced to ground which allows the... | 07/02/2002 |
| 6414359 | Six transistor SRAM cell having offset p-channel and n-channel transistors A 6T CMOS SRAM cell (100) that increases process margins for a given cell area The cell (100) comprises a pair of cross-coupled inverters (102, 104). Each inverter (102, 104) comprises a p-channel pull-up transistor (106, 108) and a n-channel pull-down tr... | 07/02/2002 |
| 6396109 | Isolated NMOS transistor fabricated in a digital BiCMOS process A method for making an isolated NMOS transistor (10) in a BiCMOS process includes forming an N- conductivity type DUF layer (19) in a P conductivity type semiconductor substrate (12), followed by forming alternate contiguous N+ and P conductivity type bur... | 05/28/2002 |
| 6393048 | Method for the transferring a digital data signal using spread spectrum In the method for the transfer of a digital data signal with predetermined band width from a transmitter to a receiver, the spread spectrum technique is used. In the method, the data signal is modulo-2 added with a PN code sequence, the bit rate of which ... | 05/21/2002 |
| 6381564 | Method and system for using response-surface methodologies to determine optimal tuning parameters for complex simulators A method and system for providing optimal tuning for complex simulators. The method and system include initially building at least one RSM model having input and output terminals. Then there is provided a simulation-free optimization function by construct... | 04/30/2002 |
