Did You Know...
...that in 1800 ether was first used by partyers as a fun diversion? Sniffing the gas led to hilarious and raucous laughter as people watched each other become more and more intoxicated and silly. Several doctors independently realized the value ether would have to anesthetize surgery patients. Of those who claimed rights to the "discovery," none had a happy ending. One had a seizure and died defending his rights. Another spent his life in an asylum because he had been denied acclaim. A third became addicted to chloroform and, in a New York City jail, he soaked a cloth in the drug, severed an artery and bled to death.
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| Number | Title | Issue Date |
| 8184474 | Asymmetric SRAM cell with split transistors on the strong side An integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary NMOS driver or PMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor. An integrated circuit containing an SRAM cell array in w... | 05/22/2012 |
| 8183621 | Non-volatile memory cell having a heating element and a substrate-based control gate The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The progr... | 05/22/2012 |
| 8183137 | Use of dopants to provide low defect gate full silicidation The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming a layer of gate electrode material over a layer of gate dielectric material, wherein the la... | 05/22/2012 |
| 8183117 | Device layout in integrated circuits to reduce stress from embedded silicon-germanium An integrated circuit including one or more transistors in which source and drain regions are formed as embedded silicon-germanium (eSiGe). Guard ring structures in the integrated circuit are formed in single-crystal silicon, rather than in eSiGe. In one example, p-... | 05/22/2012 |
| 8179775 | Precoding matrix feedback processes, circuits and systems An electronic device includes a first circuit (111) operable to generate a precoding matrix index (PMI) vector associated with a plurality of configured subbands, and further operable to form a compressed PMI vector from the PMI vector wherein the compressed ... | 05/15/2012 |
| 8179715 | 8T SRAM cell with four load transistors An integrated circuit containing SRAM cells with auxiliary load transistors on each data node. The integrated circuit also contains circuitry so that auxiliary load transistors in addressed SRAM cells may be biased independently of half-addressed cells. A process of... | 05/15/2012 |
| 8178915 | Unitary floating-gate electrode with both N-type and P-type gates An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-... | 05/15/2012 |
| 8176241 | System and method for optimizing DRAM refreshes in a multi-channel memory controller In accordance with the teachings of the present invention, a system and method for optimizing DRAM refreshes in a multi-channel memory controller are provided. In a particular embodiment, the method includes receiving, at a router in a light modulation system, a sig... | 05/08/2012 |
| 8174914 | Method and structure for SRAM Vmin/Vmax measurement A parametric test circuit is disclosed (FIG. 8B). The test circuit includes a latch circuit having true and complementary terminals. A first access transistor (206) has a current path connected between the true terminal and a first access terminal (... | 05/08/2012 |
| 8174884 | Low power, single poly EEPROM cell with voltage divider An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIGS. 7 and 8) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (806) coupled to receive... | 05/08/2012 |
| 8174248 | Systems and methods of bit stuffing pulse width modulation Systems and methods for bit stuffing pulse width modulation are provided. Example embodiments of the systems and methods of bit stuffing pulse width modulation disclosed herein may allow for a significant reduction in the size of the bootstrap capacitor while giving... | 05/08/2012 |
| 8174209 | DC-DC converter and method for minimizing battery peak pulse loading The invention relates to an electronic device, comprising a DC-DC converter for converting a primary supply voltage into an output voltage at an output node to be coupled to a super capacitor and a control stage for operating the regulated DC-DC converter in a forwa... | 05/08/2012 |
| 8173510 | Lateral drain-extended MOSFET having channel along sidewall of drain extension dielectric An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor... | 05/08/2012 |
| 8171804 | Motion conversion system A motion conversion system is described. The motion conversion system comprises a first torsional member operative for rotating in a first direction. A second torsional member is offset a distance from the first torsional member, wherein the second torsional member ... | 05/08/2012 |
| 8171333 | Sub-beam forming transmitter circuitry for ultrasound system Multi-channel pulser driver circuitry for a sub-beam forming transmitter of an ultrasound system in which sub-beam signals are formed by delaying sub-beam pulse pattern data in accordance with sub-beam pulse delay data and multiple clock signals. ... | 05/01/2012 |
| 8170858 | Characterization and modeling of ferroelectric capacitors Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. ... | 05/01/2012 |
| 8170356 | Linear temporal reference scheme having non-reference predictive frames The method, system, and apparatus of linear temporal reference scheme having non-reference predictive frames is disclosed. In one embodiment, a method of a temporal reference scheme includes creating a non-reference predictive frame and a reference predictive frame ... | 05/01/2012 |
| 8166286 | Data pipeline with large tuning range of clock signals The invention relates to a data pipeline comprising a first stage with a data input for receiving a digital data input signal, a clock input and a data output, and a first bi-stable element being adapted to be switched in response to an edge of a first clock signal,... | 04/24/2012 |
| 8165202 | Video compression rate The video encoding rate control with the quantization parameter for basic units of macroblocks of a picture adapting to deviation from the average quantization parameter over pictures of the same type (i.e., I-pictures, P-pictures, and B-pictures). ... | 04/24/2012 |
| 8164945 | 8T SRAM cell with two single sided ports A dual port SRAM cell includes an auxiliary driver transistor on each data node. The SRAM cell is capable of single sided write to each data node. The auxiliary driver transistors in addressed cells may be biased independently of half-addressed cells. During write a... | 04/24/2012 |
| 8164386 | Methods and apparatus to control rail-to-rail class AB amplifiers In one example, an amplifier for providing stable output quiescent current comprising includes a number of supply rails, an output device configured for providing an output voltage, the output device coupled to the plurality of supply rails, and an output quiescent ... | 04/24/2012 |
| 8164364 | Circuitry and method for preventing base-emitter junction reverse bias in comparator differential input transistor pair A differential input circuit (1-1) includes first (Q0) and second (Q1) input transistors having control electrodes coupled to first (Vin+) and second (Vin−) input signals, respectively. A pass... | 04/24/2012 |
| 8160872 | Method and apparatus for layered code-excited linear prediction speech utilizing linear prediction excitation corresponding to optimal gains A layered code-excited linear prediction (CELP) encoder, an Adaptive Multirate Wideband (AMR-WB) encoder and methods of CELP encoding and decoding. In one embodiment, the encoder includes: (1) a core layer subencoder and (2) at least one enhancement layer subencoder... | 04/17/2012 |
| 8160150 | Method and system for rate distortion optimization Method, video encoders, and digital systems are provide in which motion vector determination includes selecting a plurality of candidate motion vectors for a macroblock using a cost function including both a block distortion measure and a motion vector cost measure ... | 04/17/2012 |
| 8160144 | Video motion estimation Motion estimation in video encoding switches among motion estimation methods for successive predicted pictures depending upon statistics of prior pictures. Locally averaged motion vectors, fraction of intra-coded macroblocks, average quantization parameter, and so f... | 04/17/2012 |
| 8160136 | Probabilistic bit-rate and rate-distortion cost estimation for video coding A method of video encoding is provided that includes computing spatial variance for video data in a block of a video sequence, estimating a first bit-rate based on the spatial variance, a transform coefficient threshold, and variance multiplicative factors empirical... | 04/17/2012 |
| 8160117 | Line rate spread spectrum clock generator for use in line imaging systems A method of generating a spread spectrum clock signal for a line imaging device including receiving a line length value of the line imaging device, receiving a first clock signal indicative of a system timing signal in the line imaging device, generating a spreading... | 04/17/2012 |
| 8159863 | 6T SRAM cell with single sided write An SRAM cell containing an auxiliary driver transistor is configured for a single sided write operation. The auxiliary driver transistor may be added to a 5-transistor single-sided-write SRAM cell or to a 7-transistor single-sided-write SRAM cell. The SRAM cell may ... | 04/17/2012 |
| 8159382 | Low power converter and shutdown SAR ADC architecture With Successive Approximation Register (SAR) analog-to-digital converters (ADCs), there are several different architectures. One of these architectures is a “convert and shut down” architecture, where an internal amplifier is powered down during the sampling pha... | 04/17/2012 |
| 8159244 | Method and system for testing a semiconductor package A method and system for testing a semiconductor package. At least some of the illustrative embodiments are methods comprising testing a semiconductor package unit (150, 420) by electrically coupling a top printed circuit board (208, 420) to a top-side ... | 04/17/2012 |
| 8159207 | Low drop voltage regulator with instant load regulation and method An LDO regulator (10) produces an output voltage (Vout) by applying the output voltage to a feedback input (6) of a differential input stage (10A) and applying an output (3) of the differential input stage to a gate of a first follower tr... | 04/17/2012 |
| 8159199 | On-chip voltage supply scheme with automatic transition into low-power mode of MSP430 An integrated electronic device includes circuitry for providing a system supply voltage from a primary power supply. The circuitry has a high power (HP) stage coupled to the primary power supply and having an output node coupled to a supply system node for providin... | 04/17/2012 |
| 8157388 | System and method for a projection display system using an optical lightguide A system and method for using an optical lightguide in a projection display system. A plurality of light sources provides a plurality of colored light to a lightguide. The lightguide may include alternating layers of a relatively high refractive index material and a... | 04/17/2012 |
| 8155164 | Spread frequency spectrum waveform generating circuit The objective of this invention is to provide a circuit that generates a spread frequency spectrum waveform with shaped frequency spectrum distribution. The waveform generator has a spread spectrum waveform generating circuit that generates a waveform with a spread ... | 04/10/2012 |
| 8154938 | Memory array power domain partitioning An integrated circuit containing a nonvolatile memory circuit which contains memory segments and sense amplifier banks individually powered by a power decoder circuit. A method of accessing a portion of a powered-down memory. ... | 04/10/2012 |
| 8154350 | PLL with continuous and bang-bang feedback controls An apparatus is provided. The apparatus comprising a voltage controlled oscillator (VCO), an amplifier, a switch, a calibration capacitor, and a control loop. The VCO includes a capacitive network that receives a first tuning voltage that is based at least in part o... | 04/10/2012 |
| 8154337 | Apparatus and method for automated offset reduction in matched differential input devices An amplifier includes an input stage, a comparator coupled to an output of the differential input stage, and a trimming controller coupled to an output of the comparator. The input stage includes a plurality of trim devices coupled in parallel with a first input dev... | 04/10/2012 |
| 8154253 | Cell voltage abnormality detector and cell voltage monitoring device for a multi-cell series battery A circuit for detecting battery cell abnormalities in a multi-cell series battery for effectively and quickly detecting abnormalities with a simple, small circuit that provides improved reliability, safety and service life of the multi-cell series battery. In the vo... | 04/10/2012 |
| 8154222 | Pulse-width modulation current control with reduced transient time One embodiment of the present invention includes a current regulator circuit. The circuit includes at least one switch configured to periodically couple and decouple a respective at least one voltage rail to an inductor to maintain a current through the inductor. Th... | 04/10/2012 |
| 8154101 | High voltage diode with reduced substrate injection A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is pre... | 04/10/2012 |
