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| Number | Title | Issue Date |
| 7220600 | Ferroelectric capacitor stack etch cleaning methods Methods (100) are provided for fabricating a ferroelectric capacitor structure including methods (128) for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The methods comprise etching (140, 200) porti... | 05/22/2007 |
| 7221190 | Differential comparator with extended common mode voltage range A system and method is provided for extending the range of a common mode voltage of a differential comparator. In one embodiment, a differential comparator comprises an input stage with a negative voltage reference node, a first differential input coupled to a first... | 05/22/2007 |
| 7217626 | Transistor fabrication methods using dual sidewall spacers Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure (114), after which a source/drain region (116) is impla... | 05/15/2007 |
| 7217322 | Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped silicon-germanium layer, wherein arsenic and germanium are introduced subsequently into different regions of... | 05/15/2007 |
| 7216247 | Methods and systems to reduce data skew in FIFOs The disclosed invention provides methods and systems for writing and reading data in systems using multiple FIFO buffer elements. For each buffer element, a determination is made of when the rising edge of the read clock occurs during the second half of the write cl... | 05/08/2007 |
| 7216272 | Method for reducing SRAM test time by applying power-up state knowledge Methods (400, 500, and 600) are disclosed for testing a memory device by tailoring an algorithm (460) used in the testing based on the preferred or intrinsic data state 425 that is obtained upon power-up of an advanced technology SRAM mem... | 05/08/2007 |
| 7216310 | Design method and system for optimum performance in integrated circuits that use power management The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory tra... | 05/08/2007 |
| 7215000 | Selectively encased surface metal structures in a semiconductor device The present invention provides, in one embodiment, An integrated circuit device (100). The integrated circuit device (100) comprises a circuit feature (105) located over a semiconductor substrate (110) and an insulating layer (115)... | 05/08/2007 |
| 7214609 | Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities Methods are disclosed for forming trench or via cavities in a single damascene interconnect structure, comprising etching a dielectric layer to form a cavity there and to expose an underlying etch-stop layer, and etching the exposed etch-stop layer to extend the cav... | 05/08/2007 |
| 7214550 | Method to produce thin film resistor using dry etch A method of fabricating a thin film resistor (100). The resistor material (104), e.g., NiCr, is deposited. A hard mask material (106), e.g., TiW, may be deposited over the resistor material (104). The resistor material (104) and ha... | 05/08/2007 |
| 7215458 | Deflection mechanisms in micromirror devices A method and apparatus for operating spatial light modulator have been disclosed herein. The spatial light modulator comprises an array of micromirror devices, each of which further comprises a reflective deflectable mirror plate attached to a deformable hinge, and ... | 05/08/2007 |
| 7211516 | Nickel silicide including indium and a method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nicke... | 05/01/2007 |
| 7212931 | Electric energy meter for an AC mains supply An energy consumption meter having a variable phase error compensator. While the variable phase error compensator may provide fixed phase error compensation for fixed phase error(s), it may also provide variable compensation for varying phase error(s) introduced by ... | 05/01/2007 |
| 7212607 | X-ray confocal defect detection systems and methods An x-ray confocal defect detection system comprises an x-ray source, a confocal component, and defect detectors and operates on a target portion of a semiconductor device. The x-ray source generates x-ray energy. The semiconductor device includes a plurality of form... | 05/01/2007 |
| 7212387 | Electrostatic discharge protection device including precharge reduction ESD protection circuitry for a signal power supply pad (801) comprising a discharge circuit (802) operable to discharge the ESD pulse to ground, and a precharge reduction circuit (810) in parallel with the discharge circuit. This precharge reduc... | 05/01/2007 |
| 7212359 | Color rendering of illumination light in display systems A method and a color rendering filter for compensating for deficiency in illumination light from a light source in display systems are provided. The color rendering filter has a color that is determined based upon the spectrum, sensitivity of viewer's eyes over the ... | 05/01/2007 |
| 7212059 | Level shift circuit The circuit is to provide a type of level shift circuit that operates correctly even when the input timings of voltages from multiple power sources are different. Level shift circuit 10 that outputs the output signal of the high voltage source as a response t... | 05/01/2007 |
| 7211481 | Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in ... | 05/01/2007 |
| 7208379 | Pitch multiplication process A method for multiplying the pitch of a semiconductor device is disclosed. The method includes forming a patterned mask layer on a first layer, where the patterned mask layer has a first line width. The first layer can then be etched to form a first plurality of slo... | 04/24/2007 |
| 7208364 | Methods of fabricating high voltage devices Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A... | 04/24/2007 |
| 7208362 | Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Carbon-doped silicon is then epitaxia... | 04/24/2007 |
| 7208330 | Method for varying the uniformity of a dopant as it is placed in a substrate by varying the speed of the implant across the substrate The present invention provides a method for placing a dopant in a substrate and a method for manufacturing an integrated circuit. The method for placing a dopant in a substrate, among other steps, includes providing a substrate (340) and implanting a dopant w... | 04/24/2007 |
| 7208388 | Thin film resistor head structure and method for reducing head resistivity variance A method of making integrated circuit thin film resistor includes forming a first dielectric layer (18B) over a substrate and providing a structure to reduce variation of head resistivity thereof by forming a dummy fill layer (9A) on the first dielectr... | 04/24/2007 |
| 7209060 | Reducing variation in reference voltage when the load varies dynamically Providing a substantially constant reference voltage to a component from a reference buffer connected by a path. The load that would be offered to the reference buffer in desired durations is estimated, and a dummy load is added to the path such that the aggregate l... | 04/24/2007 |
| 7208993 | Input current leakage correction for multi-channel LVDS front multiplexed repeaters A high-speed front-multiplexed multi-channel LVDS-compatible repeater circuit that limits input leakage current levels in the event one or more input voltages of the circuit exceeds the supply voltage. The LVDS repeater includes a multiplexor having a plurality of d... | 04/24/2007 |
| 7209005 | Class-AB amplifier for dual voltage supplies An amplifier providing a drive signal indicative of a data input signal to a capacitive and/or resistive type load, the amplifier having a first transistor circuit adapted for converting the data input signal to a corresponding current signal in which the transistor... | 04/24/2007 |
| 7208409 | Integrated circuit metal silicide method Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer i... | 04/24/2007 |
| 7208398 | Metal-halogen physical vapor deposition for semiconductor device defect reduction The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises depositing by physical vapor deposition, halogen atoms (120) and transition metal atoms (130)... | 04/24/2007 |
| 7208386 | Drain extended MOS transistor with improved breakdown robustness A drain-extended metal-oxide-semiconductor transistor (40) with improved robustness in breakdown characteristics is disclosed. Field oxide isolation structures (29c) are disposed between the source region (30) and drain contact regions ( | 04/24/2007 |
| 7208380 | Interface improvement by stress application during oxide growth through use of backside films The present invention provides, in one aspect, a method of fabricating a gate oxide layer on a microelectronics substrate. This embodiment comprises forming a stress inducing pattern on a backside of a microelectronics wafer and growing a gate oxide layer on a front... | 04/24/2007 |
| 7205749 | Power line communication using power factor correction circuits A PFC circuit modulating a power line using pulse width modulation (PWM) to drive a power MOSFET and series inductor across the power line. Since many modern electronic systems include a power factor correction circuit (PFC) that already includes a series inductor a... | 04/17/2007 |
| 7205924 | Circuit for high-resolution phase detection in a digital RF processor A novel time-to-digital converter (TDC) used as a phase/frequency detector and charge pump replacement in an all-digital PLL within a digital radio processor. The TDC core is based on a pseudo-differential digital architecture making it insensitive to NMOS and PMOS ... | 04/17/2007 |
| 7206030 | Fast-convergence two-stage automatic gain control (AGC) Disclosed are methods and systems for automatic gain control (AGC) in circuits. The disclosed methods and systems provide accurate and rapidly converging automatic gain control suited for video applications. According to disclosed preferred embodiments of the invent... | 04/17/2007 |
| 7206155 | High-speed, low power preamplifier write driver A write driver circuit (38) uses a matching resistors (R0, R1) to match the impedance of the head (32) disposed between output nodes (OUTP, OUTN). Control circuitry (Q4, Q5, Q6, Q7, R2, R4, R6 | 04/17/2007 |
| 7205736 | Method for voltage feedback for current mode linear motor driver Methods and systems for driving a motor are disclosed. A center tap voltage and a desired center tap voltage are used to generate a voltage feedback. A power amplifier receives a reference current and the voltage feedback. The power amplifier provides a phase curren... | 04/17/2007 |
| 7203797 | Memory management of local variables A processor preferably comprises a processing core that generates memory addresses to access a main memory and on which a plurality of methods operate. Each method uses its own set of local variables. The processor also includes a cache subsystem comprising a multi-... | 04/10/2007 |
| 7202533 | Thin film resistors integrated at a single metal interconnect level of die An integrated circuit structure includes a first dielectric layer disposed on a semiconductor layer, a first thin film resistor disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and the first thin film resistor,... | 04/10/2007 |
| 7199917 | Micro-mirror element with double binge According to one embodiment of the present invention a micro-mirror element comprises a lower layer, a first middle layer, a second middle layer, and a micro-mirror. The lower layer includes an address portion for receiving an address voltage and a bias portion for ... | 04/03/2007 |
| 7200027 | Ferroelectric memory reference generator systems using staging capacitors Reference generator systems (108, 130) and methods (200) are presented for providing bitline reference voltages for memory access operations in a ferroelectric memory device (102). The reference generator system (108, 130) comprises a pri... | 04/03/2007 |
| 7199471 | Method and apparatus for reducing capacitive coupling between lines in an integrated circuit An integrated circuit (78) includes a memory circuit (10, 110, 210, 310, 410) having a group of bitlines (21–28, 121–128, 221–228, 321–328, 421–428), and having an array of memory cells (11–18) which are each electrically coup... | 04/03/2007 |
