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| Number | Title | Issue Date |
| 8174545 | Mitigation of temporal PWM artifacts A system and method for reducing pulse width modulation contouring artifacts. Each input intensity value is translated to at least one non-binary bit pattern for display. Many of the input intensity values are translated to at least two alternate non-binary bit patt... | 05/08/2012 |
| 8154782 | Method and system for generating a drive signal for a MEMS scanner A method for generating a drive signal for a micro-electro-mechanical system (MEMS) scanner is provided. The method includes generating the drive signal for the MEMS scanner using a direct digital synthesis, numerically-controlled oscillator. For a particular embodi... | 04/10/2012 |
| 8148963 | Self-oscillating converter A converter has a main feedback path and two auxiliary feedback paths from an output node to an auxiliary differential input pair of a comparator. The auxiliary feedback paths have different RC time constants so that a differential ramp signal is effectively applied... | 04/03/2012 |
| 8148914 | Dynamic power saving pulse width modulated LED driver circuit In accordance with an aspect of the present invention, an LED driving circuit includes a digital-to-analog converter and a driving portion. The circuit is operable to turn off the digital-to-analog converter at times when the driving portion is not providing a high ... | 04/03/2012 |
| 8129089 | Use of blended solvents in defectivity prevention The present invention provides a blended solvent for solubilizing an ultraviolet photoresist. The blended solvent comprises a mixture of from about 5 vol % to about 95 vol % of a first solvent, wherein the first solvent comprises a cyclic ester. A balance of the mix... | 03/06/2012 |
| 8125035 | CMOS fabrication process Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverse... | 02/28/2012 |
| 8125030 | High voltage SCRMOS in BiCMOS process technologies An integrated circuit containing an SCRMOS transistor. The SCRMOS transistor has one drain structure with a centralized drain diffused region and distributed SCR terminals, and a second drain structure with distributed drain diffused regions and SCR terminals. An MO... | 02/28/2012 |
| 8111330 | Method and apparatus for analog graphics sample clock frequency offset detection and verification A method and apparatus for an analog-to-digital video signal converter. The converter is controlled by a clock with controllable frequency and phase for sampling an analog signal. A circuit corrects the clock frequency using a period of a columnar frame differences ... | 02/07/2012 |
| 8093115 | Tuning of SOI substrate doping A method of manufacturing a semiconductor device, the method comprising: taking an SOI substrate comprising a bulk substrate, a buried insulating layer and an active layer, and implanting the bulk substrate from the side of and through the insulating layer and the a... | 01/10/2012 |
| 8017439 | Dual carrier for joining IC die or wafers to TSV wafers A method of forming stacked electronic articles using a through substrate via (TSV) wafer includes mounting a first carrier wafer to a top side of the TSV wafer using a first adhesive material that has a first debonding temperature. The TSV wafer is thinned from a b... | 09/13/2011 |
| 8012879 | Etching method using an at least semi-solid media An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch reactant media may be applied to remove meta... | 09/06/2011 |
| 7999793 | Median and mean coherent filter and method for eliminating noise in touch screen controller A touch screen system includes a touch screen assembly (30,31) and a touch screen controller (1A) coupled to terminals (24,25,26,27) of the touch screen assembly (30,31), the touch screen controller (1A) including a controller (... | 08/16/2011 |
| 7999293 | Photodiode semiconductor device and manufacturing method The invention provides a semiconductor device manufactured with a plurality of photodiodes so that it does not short circuit, and includes an opening without leakage. A second semiconductor layer (12, 16) of second conductivity type is formed on a main surfac... | 08/16/2011 |
| 7952145 | MOS transistor device in common source configuration A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. F... | 05/31/2011 |
| 7932843 | Parallel CABAC decoding for video decompression A method of video decoding is provided that includes receiving a data stream comprising a sequence of syntax elements that were compressed using context-adaptive binary arithmetic coding (CABAC), such that the encoding of each bin of a bin string representative of a... | 04/26/2011 |
| 7910471 | Bumpless wafer scale device and board assembly A semiconductor chip having a planar active surface including an integrated circuit; the circuit has metallization patterns including a plurality of contact pads. Each of these contact pads has an added conductive layer on the circuit metallization. This added layer... | 03/22/2011 |
| 7902032 | Method for forming strained channel PMOS devices and integrated circuits therefrom An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate stack is formed in or on the semiconductor surface and includes a gate electrode on a gate dielectric, wher... | 03/08/2011 |
| 7898275 | Known good die using existing process infrastructure An apparatus for testing a semiconductor die and the method wherein there is provided a package having a cavity therein with a plurality of terminals in the package disposed at the periphery of the cavity. A semiconductor die to be tested and having a plurality of b... | 03/01/2011 |
| 7897410 | Close proximity scanning surface contamination analyzer Reducing chemical contaminants is increasingly important for maintaining competitive production costs during fabrication of electronic devices. There is currently no production floor capability for mapping chemical contaminants across an electronic device substrate ... | 03/01/2011 |
| 7846783 | Use of poly resistor implant to dope poly gates A process of fabricating an IC is disclosed in which a polysilicon resistor and a gate region of an MOS transistor are implanted concurrently. The concurrent implantation may be used to reduce steps in the fabrication sequence of the IC. The concurrent implantation ... | 12/07/2010 |
| 7868690 | Comparator with sensitivity control A comparator has a differential input stage, a current source coupled to the differential input stage for providing a tail current to one side of the differential input stage, and a differential load coupled to the differential pair and having at least one diode cou... | 01/11/2011 |
| 7863103 | Thermally improved semiconductor QFN/SON package A semiconductor device without cantilevered leads uses conductive wires (120) to connect the chip terminals to the leads (110), and a package compound (140) to encapsulate the chip surface (101a) with the terminals, the wires, and ... | 01/04/2011 |
| 7855432 | Integrated thermal characterization and trim of polysilicon resistive elements Devices, systems, and methods for providing an on-chip, temperature-stable resistance network for generating a precision current or precision resistance are disclosed. The resistance network includes a first resistance material having a linear, negative temperature ... | 12/21/2010 |
| 7851928 | Semiconductor device having substrate with differentially plated copper and selective solder A semiconductor device having an insulating substrate with differentially plated metal and selective solder. Chip 221 with contact studs 223 is attached onto the traces 203 on tape 101. The traces, which are unprotected by soldermask 1... | 12/14/2010 |
| 7843261 | Resistor network for programmable transconductance stage A voltage-to-current converter is provided. The voltage-to-current converter comprises an amplifier, a resistor network, an R-2R network, and switches. The amplifier has a first input node (which is an input signal), a second input node, and an output node. The resi... | 11/30/2010 |
| 7842567 | Dual work function CMOS devices utilizing carbide based electrodes Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the met... | 11/30/2010 |
| 7840827 | Display power management An apparatus and method for power management of a display system. A display controller couples to a memory storage device. A frame buffer in the memory storage device is filled with frames of information for display on a display device. The frames of information tra... | 11/23/2010 |
| 7838924 | MOS device with substrate potential elevation An integrated circuit (25) formed at a semiconducting surface of a substrate including a common p-layer (38) includes functional circuitry (24) formed on the p-layer (38) including a plurality of terminals (IN, OUT, I/O) coupled to the fu... | 11/23/2010 |
| 7834636 | Methods and apparatus to facilitate ground fault detection with a single coil A ground fault detection device includes a sense coil including a primary winding and a secondary winding to detect current in a line conductor and a neutral conductor. It also includes a capacitor in parallel with the secondary winding and a virtual inductor to for... | 11/16/2010 |
| RE41830 | Oversampling analog-to-digital converter and method with reduced chopping residue noise A delta-sigma modulator includes a chopper-stabilized integrator, a quantizer having an input coupled to an output of the integrator, an input signal acquiring circuit controlled by a switched reference feedback circuit and having an output coupled to the input of t... | 10/19/2010 |
| 7772057 | Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are forme... | 08/10/2010 |
| 7768850 | System for bitcell and column testing in SRAM A system comprises a storage cell coupled to multiple bitlines and a transistor that couples to the multiple bitlines in parallel with the storage cell. The transistor is activated while the storage cell is read. ... | 08/03/2010 |
| 7737015 | Formation of fully silicided gate with oxide barrier on the source/drain silicide regions A simple and cost effective method of forming a fully silicided (FUSI) gate of a MOS transistor is disclosed. In one example, the method comprises forming a nitride hardmask overlying a polysilicon gate, forming an S/D silicide in source/drain regions of the transis... | 06/15/2010 |
| 7727838 | Method to improve transistor Tox using high-angle implants with no additional masks A method of forming an integrated circuit includes forming a gate structure over a semiconductor body, and forming a shadowing structure over the semiconductor body laterally spaced from the gate structure, thereby defining an active area in the semiconductor body t... | 06/01/2010 |
| 7724101 | Crystal oscillator circuit with amplitude control A crystal oscillator circuit includes a capacitive load stage coupled to a crystal; an amplifier stage including an amplifying transistor coupled to the crystal and to the capacitive load stage for establishing an oscillation signal at the amplifier stage output and... | 05/25/2010 |
| 7678675 | Structure and method for a triple-gate transistor with reverse STI Exemplary embodiments provide triple-gate semiconductor devices isolated by reverse STI structures and methodologies for their manufacture. In an exemplary process, stacked layers including a form layer over a dielectric layer can be formed over a semiconductor subs... | 03/16/2010 |
| 7676698 | Apparatus and method for coupling a plurality of test access ports to external test and debug facility An interface unit is provided for selectively testing a plurality of processor/cores. The interface unit includes an interface test access port (TAP) unit operable to receive test commands, and a logic unit coupled to the interface TAP unit and operable to generate ... | 03/09/2010 |
| 7675272 | Output impedance compensation for linear voltage regulators In a method and system for regulating an output voltage, a linear voltage regulator (LVR) includes an adjustable shunt regulator (ASR) having a limited gain, a feedback circuit (FC), and a compensation resistor (CR). The limited gain causes the output voltage of the... | 03/09/2010 |
| 7671445 | Versatile system for charge dissipation in the formation of semiconductor device structures The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might resul... | 03/02/2010 |
| 7668313 | Recipient-encrypted session key cryptography A method for protecting secret keys, such as HDCP device key sets, during the manufacturing process is disclosed. In particular, the present invention comprises a method for securely sending and receiving data, such as HDCP device key sets, for use in a cryptosystem... | 02/23/2010 |
