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| Number | Title | Issue Date |
| 5084873 | Chip error detector A memory cell system is disclosed with properties of asymmetrical operation such that the occurrence of memory error due to certain environmental disturbances is detectable. The asymmetry of operation can be adjusted to set the level at which the disturba... | 01/28/1992 |
| 5053848 | Apparatus for providing single event upset resistance for semiconductor devices A method for preventing single event upsets (SEUs) in MOS circuits is disclosed. A resistive area (88, 89) is situated in a semiconductor device such that when a high energy particle passes through the device and the resistive area (88, 89) the stray carr... | 10/01/1991 |
| 5047670 | BiCMOS TTL input buffer A threshold control BiCMOS TTL input buffer is disclosed which substantially eliminates input trip point variation across power supply, process, and temperature and additionally minimizes buffer power dissipation.... | 09/10/1991 |
| 5045490 | Method of making a pleated floating gate trench EPROM One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to incre... | 09/03/1991 |
| 5046044 | SEU hardened memory cell A memory cell is disclosed comprising cross-coupled inverters including gated diodes connected in the cross-coupling which increase the memory cell's resistance to single event upset. The layouts for constructing such a memory cell, which optimize READ an... | 09/03/1991 |
| 4983226 | Defect free trench isolation devices and method of fabrication The specification discloses an isolation trench (36) formed in a semiconductor body. A stress relief layer (38) of oxide is formed on the interior walls of the trench (36), the layer (38) being sufficiently thin to prevent stressing of the lower corners o... | 01/08/1991 |
| 4946799 | Process for making high performance silicon-on-insulator transistor with body node to source node connection A process for making a silicon-on-insulator MOS transistor is disclosed which includes forming an implanted region on the source side of the gate electrode for making contact to the body node. A contact region of the same conductivity type as the body nod... | 08/07/1990 |
