Bizarre Patents
User-operated amusement apparatus for kicking the user's buttocks
An apparatus including a user-operated and controlled apparatus for self-infliction of repetitive blows to the user's buttocks by a plurality of elongated arms bearing flexible extensions that rotate under the user's control.
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| Number | Title | Issue Date |
| 6397720 | Cartridge case reforming die having precise measuring system A novel resizing die (100/300) for a cartridge case has been provided for efficiently and quickly resizing a cartridge case during a reloading operation. The novel die includes a precise measuring system (122, 124, 108/122, 306, 108) for being able to acc... | 06/04/2002 |
| 5928295 | Method and apparatus for automatic calibration of the wheel track of a movable vehicle This invention reduces the navigation error associated with the use of wheel sensor based DR as an augmentation to GPS. In order to derive accurate heading information from the wheel speeds, the distance between the centers of the tires, or the wheel trac... | 07/27/1999 |
| 5862132 | System and method for multiple access short message communications The present invention describes a communications system that utilizes frequency division multiple access (FDMA), code division multiple access (CDMA), and time division multiple access (TDMA) techniques for providing efficient use of frequency spectrum wh... | 01/19/1999 |
| 5826189 | Cellular communication system with efficient channel assignments and method therefor A cellular communication system (10) forms cells (18) from low earth orbit satellites (12). The system (10) uses an off-line process (24) to identify cells (18) that fall within various reuse distances of other cells (18) and to save system usage statisti... | 10/20/1998 |
| 5809036 | Boundary-scan testable system and method A system (10) includes any number of Boundary-Scan integrated circuits (28), a common bus (14), and a Boundary-Scan master (22). The integrated circuits (28) include mode selection logic (58) that isolates pins (30, 32) from core logic (34) during Capture... | 09/15/1998 |
| 5784029 | Recognition of and method and apparatus for GPS antenna lever arm compensation in integrated GPS/dead reckoning navigation systems This invention reduces the error growth associated with vehicle Dead Reckoning (DR) systems utilizing heading rate sensors (15) by compensating for the lever arm or offset between the Global Positioning System (GPS) antenna (11) and the center of rotation... | 07/21/1998 |
| 5778416 | Parallel process address generator and method A memory linked address generator and method for a complex arithmetic processor executing an algorithm sequence includes memories, a clock for generating a clock cycle, and a decoder for determining position of the complex arithmetic processor within the ... | 07/07/1998 |
| 5774833 | Method for syntactic and semantic analysis of patent text and drawings A method for processing patent text (99) in a computer (200) including identifying boundaries of parts of patent text (100), loading at least one of the parts of the patent text into a working memory (102), analyzing at least one of the parts of the paten... | 06/30/1998 |
| 5752220 | Method for heading error suppression in dead reckoning systems A method for substantially reducing the error that accumulates in dead reckoning systems. The method includes determining heading changes from a dead reckoning system (10), testing for improbable heading changes (20), and setting to zero any invalid headi... | 05/12/1998 |
| 5751718 | Simultaneous transfer of voice and data information using multi-rate vocoder and byte control protocol A technique and method that efficiently and simultaneously transfers both voice and data information over a single communications link (11). The technique and method utilizes a multi-rate vocoder (12) for providing voice information at a plurality of diff... | 05/12/1998 |
| 5745868 | Method for rapid recovery from dead reckoning system heading loss A method of recovering the heading of a terrestrial vehicle navigation system having a GPS receiver integrated with a dead reckoning system. After determining that a current estimate of the heading may be in error (12, 14), Doppler measurement double diff... | 04/28/1998 |
| 5745579 | Cellular telephone security adapter and method An adapter (10) for a cellular telephone includes a first coupling apparatus (21) disposed on a first surface (30) of the adapter (10). The first coupling apparatus (21) is for engaging coupling apparatus disposed on a rear surface of the cellular telepho... | 04/28/1998 |
| 5721782 | Partitioned echo canceler utilizing decimation echo location The present invention includes an adaptive filter (40) for use within an echo canceler. The adaptive filter operates in a first mode for performing Decimation Echo Location (DEL). During the DEL mode, high energy regions occurring within the echo impulse ... | 02/24/1998 |
| 5703903 | Method and apparatus for adaptive filtering in a high interference environment A method and apparatus for performing adaptive filtering in a high interference environment, such as for a radio, modem, or local area network. The adaptive filtering simultaneously provides interference excision while canceling resultant distortion in th... | 12/30/1997 |
| 5646627 | Method and apparatus for controlling a biphase modulation to improve autocorrelation in pseudorandom noise coded systems This invention relates to a method and apparatus for controlling a biphase modulator (602, 702) to improve autocorrelation in pseudorandom noise coded systems. The biphase modulator modulates a carrier frequency with one of two phase states responsive to ... | 07/08/1997 |
| 5629929 | Apparatus for rapid interference cancellation and despreading of a CDMA waveform A receiver performs rapid adaptive interference canceling for use in despreading multiple CDMA channels sharing the same RF front end. The receiver includes a buffer (22) for providing for overlapping time samples and rate adaptation, a windowing function... | 05/13/1997 |
| 5588059 | Computer system and method for secure remote communication sessions A computer system includes a Key Certification Agency (KCA) (12), a host computer (16), and a number of remote terminals (14). The KCA (12) uses incompatible encryption processes (96, 98) to encrypt session control data and to store the data as various me... | 12/24/1996 |
| 5584067 | Dual traveling wave resonator filter and method A dual traveling wave resonator filter includes a microstrip line to receive an input signal at a first end and first and second traveling wave resonator rings. Each traveling wave resonator ring is in close proximity to the microstrip line such that firs... | 12/10/1996 |
| 5578961 | MMIC bias apparatus and method A microwave monolithic integrated circuit (MMIC) RF-generated bias circuit and method includes an input for receiving an RF signal. A rectifier coupled to the input and to electrical ground produces a rectified RF signal in response. A voltage divider cou... | 11/26/1996 |
| 5371415 | Two stage gate drive circuit for a FET A two stage gate drive circuit (10) for controlling a power transistor (12) has been provided. The drive circuit includes a first stage (14) coupled to a first supply voltage terminal for providing a high current drive signal to the power transistor for q... | 12/06/1994 |
| 5327016 | Load control circuit including automatic AC/DC discernment A control circuit for switching AC or DC loads and for automatically discerning the presence of an AC or a DC power supply via a switch has been provided. The control circuit is coupled to alternately render a switch operative and non-operative wherein th... | 07/05/1994 |
| 5317211 | Programmable pin for use in programmable logic devices A buffer circuit for programming an I/O pin of a programmable logic device to function either as a normal I/O site, a power pin, or a ground pin has been provided. The I/O pin may be programmed by a user by simply placing first and second control signals ... | 05/31/1994 |
| 5304953 | Lock recovery circuit for a phase locked loop A circuit (10) for providing recovery of a phase locked loop circuit when lock has been lost has been provided. The circuit includes a lock indicator circuit (24) for detecting when the phase locked loop circuit has lost lock on an input reference signal.... | 04/19/1994 |
| 5304860 | Method for powering down a microprocessor embedded within a gate array An interface circuit (14) that allows for a flexible three-way interface between a microprocessor (12), an ASIC cell block (16), and the external world has been provided wherein the microprocessor and the ASIC cell block are fabricated within a gate array... | 04/19/1994 |
| 5304958 | Saw oscillator gain amplifier with auto phase shift A gain stage for providing an automatic phase shift is provided. In particular, the gain stage detects whether an oscillation signal appears at its inputs. If an oscillation signal is not detected, then the gain stage inverts output signals occurring at o... | 04/19/1994 |
| 5299460 | Pressure sensor A circuit for a pulse width modulating a sensor (12) has been provided. The circuit includes a first switch (22) for alternately coupling the sensor between first and second supply voltage terminals. The circuit also includes second (24) and third (28) sw... | 04/05/1994 |
| 5291075 | Fault detection circuit A circuit for detecting when a fault condition has occurred includes an input stage responsive to a logic signal supplied to an input of the circuit for providing an output logic signal at an output thereof. An output stage, including a pulldown circuit, ... | 03/01/1994 |
| 5285346 | Current driven control circuit for a power device A control circuit for protecting a power device has been provided. The control circuit has a thermal shutdown circuit for activating a first SCR when the temperature of the control circuit exceeds a predetermined temperature. Additionally, the control cir... | 02/08/1994 |
| 5283753 | Firm function block for a programmable block architected heterogeneous integrated circuit A block architected integrated circuit having a predetermined power and signal grid structures is provided. The integrated circuit includes a plurality of function blocks such as firm function blocks, standard cell logic blocks, and gate array logic block... | 02/01/1994 |
| 5272531 | Automatic gain control system for use in positive modulation which detects the peak white voltage level slowly while simultaneously adjusting black voltage level fluctuations quickly An AGC system for use in positive modulation schemes of video signals is provided. The AGC system utilizes an IF amplifier, a demodulator, a video amplifier, a gated amplifier and a peak detector. The gated amplifier has a first, relatively fast, time con... | 12/21/1993 |
| 5270585 | Output driver stage with two tier current limit protection An output driver stage (10) having current limit protection has been provided. The output driver stage provides current protection for both itself and for an output load which may be coupled to an output terminal (12). The current limit protection is acco... | 12/14/1993 |
| 5264784 | Current mirror with enable A current mirror circuit that can be disabled has been provided. An enable signal is applied to the base of a transistor that drives the common bases of an emitter-coupled pair of transistors. A voltage level of the enable signal may be used to turn off t... | 11/23/1993 |
| 5257155 | Short-circuit proof field effect transistor A protection circuit for providing short-circuit protection for a field effect transistor has been provided. The protection circuit senses when the voltage appearing at the gate and drain electrodes of the field effect transistor are both at a logic high ... | 10/26/1993 |
| 5245298 | Voltage controlled oscillator having cascoded output A voltage controlled oscillator (VCO) circuit having a cascoded output stage has been provided. The VCO circuit includes an oscillation stage which utilizes a negative resistance technique for oscillation, and an output stage that is coupled in cascode wi... | 09/14/1993 |
| 5235215 | Memory device for use in power control circuits A memory circuit which includes a memory SCR and an output SCR is provided. The memory SCR is coupled between the input terminal and the common terminal of the memory circuit wherein the input terminal is the control terminal of the output SCR and the out... | 08/10/1993 |
| 5230013 | PLL-based precision phase shifting at CMOS levels A circuit for generating precise, phase shifted, CMOS level output signals with respect to an input data signal has been provided. The circuit utilizes a phase-locked loop for generating a precise clock signal. This precise clock signal is then utilized t... | 07/20/1993 |
| 5229759 | Auto-offset LCD vertical scroll mechanism A LCD vertical scrolling mechanism automatically tracks addresses of information scrolled on a LCD. A counter is initialized to a value latched in a vector register when a frame signal is received. Subsequent BPCLK signals step the adder through a series ... | 07/20/1993 |
| 5206571 | Stepper motor controllers A driver for a stepper motor including means (Q45, 45, 47, 402) for sampling the current in a motor winding (43) at an instant determined by means (401, 400)for generating a predetermined delay following winding commutation. The sample is compared with wi... | 04/27/1993 |
| 5202626 | On-chip self-test circuit An on-chip self-test circuit has been provided that allows for accurately testing a device such as prescaler at high frequencies. The on-chip self-test circuit includes a voltage controlled oscillator for providing high frequency signals to the device und... | 04/13/1993 |
| 5202627 | Pedaling monitor for displaying instantaneous pedal velocity and position A circuit for producing a display indicative of a bicycle rider's pedaling technique. The circuit measures the time required for the pedals to move through a given angle of rotation. The circuit then calculates the relative pedal velocity over the angle o... | 04/13/1993 |
