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| Number | Title | Issue Date |
| 8030707 | Semiconductor structure A method of forming a silicon-on-insulator (SOI) semiconductor structure in a substrate having a bulk semiconductor layer, a buried oxide (BOX) layer and an SOI layer. During the formation of a trench in the structure, the BOX layer is undercut. The method includes ... | 10/04/2011 |
| 7987584 | Article extraction / insertion tool and assembly A tool assembly for removing an article from, or inserting an article onto, a printed circuit board which includes a tool housing having a handle portion and an article receiving portion, a plate slidable within the housing, the plate having a handle portion at a fi... | 08/02/2011 |
| 7939369 | 3D integration structure and method using bonded metal planes A method of making 3D integrated circuits and a 3D integrated circuit structure. There is a first semiconductor structure joined to a second semiconductor structure. Each semiconductor structure includes a semiconductor wafer, a front end of the line (FEOL) wiring o... | 05/10/2011 |
| 7875972 | Semiconductor device assembly having a stress-relieving buffer layer Disclosed is a multilayer thermal interface material which includes a first layer of metallic thermal interface material, a buffer layer and preferably a second layer of thermal interface material which may be metallic or nonmetallic. The multilayer thermal interfac... | 01/25/2011 |
| 7855137 | Method of making a sidewall-protected metallic pillar on a semiconductor substrate A method of forming conductive pillars on a semiconductor wafer in which the conductive pillars are plated with a protecting coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP. Only the side of the conductive pillars are plated. The ends of the conductive pillars ar... | 12/21/2010 |
| 7808099 | Liquid thermal interface having mixture of linearly structured polymer doped crosslinked networks and related method A liquid thermal interface (LTI) including a mixture of a linearly structured polymer doped with crosslinked networks and related method are presented. The LTI exhibits reduced liquid polymer macromolecule mobility, and thus increased surface tension. An embodiment ... | 10/05/2010 |
| 7776737 | Reliability of wide interconnects An integrated circuit which includes a semiconductor substrate, a first metal wiring level on the semiconductor substrate which includes metal wiring lines, an interconnect wiring level on the first metal wiring level which includes a via interconnect within an inte... | 08/17/2010 |
| 7759789 | Local area semiconductor cooling system A system and method in which a semiconductor chip has electrically inactive metal-filled vias adjacent to a semiconductor device or devices to be cooled and the semiconductor device or devices are preferably surrounded by thermally insulating vias. The metal-filled ... | 07/20/2010 |
| 7669159 | IC tiling pattern method, IC so formed and analysis method The invention provides a method for providing an integrated circuit (6) having a substantially uniform density between parts (10, 12, 14 and 16) of the IC that are non-orthogonally angled. In particular, the invention provides fill tiling patter... | 02/23/2010 |
| 7546400 | Data packet buffering system with automatic threshold optimization Data packet buffering system comprising a data buffer for buffering data packets, a first counter (24) preloaded with the data packet size (32) and decremented at each read clock signal of a number of logical units corresponding to the width of the out... | 06/09/2009 |
| 7501353 | Method of formation of a damascene structure utilizing a protective film Disclosed is a method for the formation of features in a damascene process. According to the method, vias are formed in a dielectric layer and then covered by a layer of high molecular weight polymer. The high molecular weight polymer covers the vias but does not en... | 03/10/2009 |
| 7496108 | Method for dynamic management of TCP reassembly buffers A method for dynamic management of Transmission Control Protocol (TCP) reassembly buffers in hardware (e.g., in a TCP/IP offload engine (TOE)). The method comprises: providing a plurality of data blocks and an indirect list; pointing, via entries in the indirect lis... | 02/24/2009 |
| 7494915 | Back end interconnect with a shaped interface An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of th... | 02/24/2009 |
| 7491588 | Method and structure for buried circuits and devices A method is provided in which for fabricating a complementary metal oxide semiconductor (CMOS) circuit on a semiconductor-on-insulator (SOI) substrate. A plurality of field effect transistors (FETs) are formed, each having a channel region disposed in a common devic... | 02/17/2009 |
| 7483434 | Parallel TCP sender implementation A system and method for providing parallel implementation of a TCP sender comprising a transmit request handler and a transmitter. A transfer control protocol (TCP) transmission system is provided, comprising: a transmit request handler that receives request events,... | 01/27/2009 |
| 7473648 | Double exposure double resist layer process for forming gate patterns A method of forming a planar CMOS transistor divides the step of forming the gate layer into a first step of patterning a resist layer with a first portion of the gate layer pattern and then etching the polysilicon with the pattern of the gates. A second step patter... | 01/06/2009 |
| 7474575 | Apparatus for testing a memory of an integrated circuit An apparatus for testing a memory of an integrated circuit for a defect. The apparatus includes a test unit for testing a redundant memory element only when the redundant memory element has been enabled to replace a failed memory element. ... | 01/06/2009 |
| 7439144 | CMOS gate structures fabricated by selective oxidation A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial polymer containing silicon that is deposited over a gate conductor layer and covered by a cover layer. The sacrificial polymer layer is patterned with convention... | 10/21/2008 |
| 7393779 | Shrinking contact apertures through LPD oxide Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to t... | 07/01/2008 |
| 7378338 | Method of forming an interconnect structure diffusion barrier with high nitrogen content In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaNx, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm. ... | 05/27/2008 |
| 7350423 | Real time usage monitor and method for detecting entrapped air A dispensing system for feeding paste through a screen onto a workpiece monitors the position of a piston applying pressure to the paste with a linear variable differential transformer and sets limits on the slope of the piston displacement is a measure of the feed ... | 04/01/2008 |
| 7343527 | Recovery from iSCSI corruption with RDMA ATP mechanism A method and system for detecting and managing an error detected in an iSCSI (Internet Small Computer System Interface) PDU (Protocol Data Unit) by using a RDMA (Remote Direct Memory Access) dedicated receive error queue for error recovery. ... | 03/11/2008 |
| 7341948 | Method of making a semiconductor structure with a plating enhancement layer Disclosed is a method of making a semiconductor structure, wherein the method includes forming an interlayer dielectric (ILD) layer on a semiconductor layer, forming a conductive plating enhancement layer (PEL) on the ILD, patterning the ILD and PEL, depositing a se... | 03/11/2008 |
| 7335461 | Method of structuring of a subtrate The invention relates to a method of structuring of a substrate by providing a polymerization starter layer on the substrate, applying a radiation field on the polymerization starter layer for selectively reducing a density of polymerization starters of the polymeri... | 02/26/2008 |
| 7329439 | UV-curable solvent free compositions and use thereof in ceramic chip defect repair Solvent-free UV-curable polymer materials derived from miscible blends of reactive organic monomeric, oligomeric and low molecular polymeric systems and organic and inorganic fillers such as polytetrafluoroethylene and talc are provided to form polymer-filler compos... | 02/12/2008 |
| 7326600 | Method for manufacturing a thin-film transistor structure The present invention provides a thin film transistor structure in which at least a trench is formed in an insulating polymer film formed on a substrate. In the thin film transistor structure, a trench formed in the insulating polymer film accommodates a gate wiring... | 02/05/2008 |
| 7325213 | Nested design approach A structure for a system of chip packages includes a master substrate and at least one subset substrate of the master substrate. The subset substrate includes a portion of the master substrate that has an identical pin out pattern as the portion of the master substr... | 01/29/2008 |
| 7320918 | Method and structure for buried circuits and devices A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component ... | 01/22/2008 |
| 7306983 | Method for forming dual etch stop liner and protective layer in a semiconductor device The present invention provides a semiconductor device having dual nitride liners, a silicide layer, and a protective layer beneath one of the nitride liners for preventing the etching of the silicide layer. A first aspect of the invention provides a method for use i... | 12/11/2007 |
| 7305334 | Methodology for image fidelity verification A method for predicting functionality of an integrated circuit segment to be lithographically printed on a wafer. Initially there is provided a two-dimensional design of an integrated circuit, including an integrated circuit segment having critical width, and a two-... | 12/04/2007 |
| 7304901 | Enabling memory redundancy during testing Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14). The memory array (14) includes general memory elements (18) and redundant memory elements (20). The general memory elements... | 12/04/2007 |
| 7298749 | Completion coalescing by TCP receiver A method and system for completion coalescing by a Transmission Control Protocol (TCP) receiver (e.g., in a TCP/IP offload engine (TOE)). The method comprises: processing inbound TCP segments; and performing completion processing of received TCP ACKS and/or RDMA Rea... | 11/20/2007 |
| 7288474 | Suspension for filling via holes in silicon and method for making the same A metallization process and material system for metallizing either blind or through vias in silicon, involving forming a low coefficient of thermal expansion composite or suspension, relative to pure metals, such as copper, silver, or gold, and filling the via holes... | 10/30/2007 |
| 7287685 | Structure and method to gain substantial reliability improvements in lead-free BGAs assembled with lead-bearing solders Methods of forming and assemblies having hybrid interconnection grid arrays composed of a homogenous mixture of Pb-free solder joints and Pb-containing solder paste on corresponding sites of a printed board. The aligned Pb-free solder joints and Pb-containing solder... | 10/30/2007 |
| 7278459 | Common carrier A method for mounting a film, used to fabricate a mask for use in screening an electronic device, to a common carrier frame. The common carrier frame has an outer edge along an outer periphery and an opening in a central portion of the frame. The method includes app... | 10/09/2007 |
| 7274612 | DRAM circuit and its operation method A high-density DRAM in a MTBL method which reduces interference noise between bit lines is provided. Duplication of sense amplifiers (SA) and bit switches (BSW) in a conventional MTBL method is eliminated, and one line of sense amplifiers and bit switches (BSW/SA) i... | 09/25/2007 |
| 7273804 | Internally reinforced bond pads Disclosed is a reinforced bond pad structure having nonplanar dielectric structures and a metallic bond layer conformally formed over the nonplanar dielectric structures. The nonplanar dielectric structures are substantially reproduced in the metallic bond layer so ... | 09/25/2007 |
| 7271681 | Clearance hole size adjustment for impedance control in multilayer electronic packaging and printed circuit boards The present invention provides a technique for adjusting the size of clearance holes for impedance control in multilayer electronic packaging and printed circuit boards. The method comprises: providing parameters for a structure having a clearance hole and at least ... | 09/18/2007 |
| 7270940 | Method of structuring of a substrate The invention relates to a method of structuring of a substrate by providing a polymerization starter layer on the substrate, applying a radiation field on the polymerization starter layer for selectively reducing a density of polymerization starters of the polymeri... | 09/18/2007 |
| 7262451 | High performance embedded DRAM technology with strained silicon Semiconductor devices are fabricated in a strained layer region and strained layer-free region of the same substrate. A first semiconductor device, such as a memory cell, e.g. a deep trench storage cell, is formed in a strained layer-free region of the substrate. A ... | 08/28/2007 |
