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| Number | Title | Issue Date |
| 5175826 | Delayed cache write enable circuit for a dual bus microcomputer system with an 80386 and 82385 In an 80386/82385 microcomputer system, the timing requirements placed on non-cache memory components by the 82385 are more stringent than the timing requirements placed on the non-cache memory components by the 80386. The present invention operates on th... | 12/29/1992 |
| 5129090 | System bus preempt for 80386 when running in an 80386/82385 microcomputer system with arbitration A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective... | 07/07/1992 |
| 5125084 | Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller Any incompatibility between pipelined operations (such as is available in the 80386) and dynamic bus sizing (allowing the processor to operate with devices of 8-, 16- and 32-bit sizes) is accommodated by use of an address decoder and ensuring that device ... | 06/23/1992 |
| 4453660 | Forms feed tractor There is disclosed herein a forms feed tractor mechanism having a belt with pins and driving elements extending threrethrough. The pins are adapted to engage perforated holes along the edge of a recorded medium. Driver means are provided for rotating the ... | 06/12/1984 |
| 4452136 | Printer subsystem with dual cooperating microprocessors A printer subsystem is interconnected with a host system from which it receives command and data information and to which it provides status information. The printer subsystem has two microprocessors, one of which communicates with the host system for tra... | 06/05/1984 |
| 4374429 | Information transfer system wherein bidirectional transfer is effected utilizing unidirectional bus in conjunction with key depression signal line An information transfer system is described that includes a central processing unit (CPU) interconnected with a peripheral device such as an operator console by an interface bus of finite capacity. Transfer of information in the system is normally in a pr... | 02/15/1983 |
| 4374417 | Method for using page addressing mechanism In a computer system, paging operates and a method of use thereof are provided for extending the addressing capability of a processor by using a page register. The page register includes means for storing different codes for different operations to be per... | 02/15/1983 |
| 4363093 | Processor intercommunication system A processor intercommunication system includes a plurality of stations which are interconnected by a transmission link, each station having an associated processor. Further, each station comprises means which provide a data link protocol mechanism for est... | 12/07/1982 |
| 4362406 | Dot matrix print head There is disclosed herein a dot matrix tilting print head assembly in which the print head is rotatably mounted in frame means. Solenoid means are provided for rotating the print head a controlled distance so that printing occurs between previously printe... | 12/07/1982 |
| 4353298 | Partial line turnaround for printers A printer is provided with facilities for increasing the printing throughput. This involves a partial line turnaround operation. The printer has means to move a form or document past a print line, a ribbon drive assembly, and a print assembly incorporatin... | 10/12/1982 |
| 4354229 | Loop initialization mechanism for a peer-to-peer communication system In a loop-structured communication system interconnecting a plurality of data processors without central controller, stations comprise modems which can start loop operation and achieve synchronous frame transmission around the loop through all participati... | 10/12/1982 |
| 4346474 | Even-odd parity checking for synchronous data transmission A synchronous data transmission system between remote stations is shown wherein data is transmitted parallel by bit serial by group over a plurality of parallel lines extending between sending and receiving stations. A parity line is also included in the ... | 08/24/1982 |
| 4284362 | Printer control logic There is disclosed herein printer control logic for controlling a matrix printer. The control logic includes an interruptable microprocessor, together with associated memory. Additionally the control logic includes a programmable timer which provides a si... | 08/18/1981 |
| 4284363 | Data matrix print head There is disclosed herein a dot matrix tilting print head assembly in which the print head is rotatably mounted in a frame. A solenoid is provided for rotating the print head a controlled distance so that printing occurs between previously printed dots. A... | 08/18/1981 |
| 4284001 | Head image generator for a matrix printer A wire matrix printer has a plurality of heads, each consisting of nine wires arranged in a slanting format. The printer can be controlled to print Oriental type characters such as Japanese by loading a wire image map of the characters into a memory. The ... | 08/18/1981 |
| 4218741 | Paging mechanism In a data processing system, a mechanism provides independent assignment of page locations for a program's instructions and its data and better enables control to be transferred between programs, or portions thereof, that reside at different addresses in ... | 08/19/1980 |
| 4200913 | Operator controlled programmable keyboard apparatus A cathode ray tube (CRT) and keyboard display terminal are operated in accordance with the program routines of a microcontroller. The microcontroller includes a random access store which is loadable by the customer during initial program load (IPL) operat... | 04/29/1980 |
| 4156796 | Programmable data processing communications multiplexer A micro processor controlled user programmable communications multiplexer subsystem (herein referred to by the symbol PCS) capable of transmitting and receiving data on any one or more of 32 communications lines simultaneously. Each line may be dynamicall... | 05/29/1979 |
| 4047161 | Task management apparatus A data processing system is described which has multiple sets of registers each of which is capable of autonomously controlling a common storage and common arithmetic and logic control circuits to execute respective tasks of a program. Level status blocks... | 09/06/1977 |
