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| Number | Title | Issue Date |
| 8185790 | Resynchronization memory in series/parallel with control/output data scan cells An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data ... | 05/22/2012 |
| 8185789 | Capturing response after simultaneously inputting last stimulus bit in scan path subdivisions Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay t... | 05/22/2012 |
| 8176374 | Data register control of TDI/AX1 to the data register The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary... | 05/08/2012 |
| 8171361 | Multiplexer Control Circuitry for TAP Domain Selection Circuitry Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap ... | 05/01/2012 |
| 8171360 | Linking module enable leads connected to plural TAPs A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20). ... | 05/01/2012 |
| 8171359 | Linking module connected to select leads of plural TAPs A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20). ... | 05/01/2012 |
| 8168970 | Die having embedded circuitry with test and test enable circuitry Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits w... | 05/01/2012 |
| 8166358 | Test access port with address and command capability The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands fo... | 04/24/2012 |
| 8161337 | Serially connected circuit blocks with TAPs and wrapper enable lead In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP b... | 04/17/2012 |
| 8156394 | Selectively accessing test access ports in a multiple test access port environment A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20). ... | 04/10/2012 |
| 8145962 | TAP interface select circuit with TMS/RCK or RCK lead This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be... | 03/27/2012 |
| 8140926 | Die selectively connecting TAP leads to second die An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC. ... | 03/20/2012 |
| 8140924 | Selectively accessing test access ports in a multiple test access port environment A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20). ... | 03/20/2012 |
| 8136003 | JTAG debug test system adapter with three sets of leads A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select regist... | 03/13/2012 |
| 8136002 | Communication between controller and addressed target devices over data signal An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin. After being enabled, the Trace domain acquires data from a functioning ci... | 03/13/2012 |
| 8132064 | Selectively accessing test access ports in a multiple test access port environment A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20). ... | 03/06/2012 |
| 8127189 | Gates and sync circuitry connecting TAP to serial communications circuitry The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal... | 02/28/2012 |
| 8122310 | Input buffer, test switches and switch control with serial I/O The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die. ... | 02/21/2012 |
| 8112685 | Serial compressed data I/O in a parallel test compression architecture The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Furthe... | 02/07/2012 |
| 8112684 | Input linking circuitry connected to test mode select and enables IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, ... | 02/07/2012 |
| 8108742 | Tap control of TCA scan clock and scan enable The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to ... | 01/31/2012 |
| 8099642 | Formatter selectively outputting scan stimulus data from scan response data The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a nov... | 01/17/2012 |
| 8099641 | Multiplexer selecting STP clock signal with tap control outputs Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection ... | 01/17/2012 |
| 8095840 | Serial scan chain in a star configuration A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configura... | 01/10/2012 |
| 8095839 | Position independent testing of circuits Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan... | 01/10/2012 |
| 8095838 | Transitioning through idle 1, 2 and sequence 1 machine states A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alter... | 01/10/2012 |
| 8094765 | Clock and mode signals controlling data communication in three states Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or sync... | 01/10/2012 |
| 8078927 | Wrapper leads gating TAP instruction and data registers In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment... | 12/13/2011 |
| 8078898 | Synchronizing TAP controllers with sequence on TMS lead A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second... | 12/13/2011 |
| 8078842 | Removing local RAM size limitations when executing software code An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first grou... | 12/13/2011 |
| 8065578 | Inverted TCK access port selector selecting one of plural TAPs The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal ter... | 11/22/2011 |
| 8065577 | Dual controllers for scan paths, distributors, and collectors Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consum... | 11/22/2011 |
| 8060027 | RF transmission leakage mitigator, method of mitigating an RF transmission leakage and CDMA transceiver employing the same The present invention provides an RF transmission leakage mitigator for use with a full-duplex, wireless transceiver. In one embodiment, the RF transmission leakage mitigator includes an inversion generator configured to provide an RF transmission inversion signal o... | 11/15/2011 |
| 8059746 | Producing STTD diversity signal from rake combined level 3 message A circuit is designed with a measurement circuit (746) coupled to receive an input signal from at least one of a first antenna and a second antenna of a transmitter. The measurement circuit produces an output signal corresponding to a magnitude of the input s... | 11/15/2011 |
| 8055967 | TAP interface outputs connected to TAP interface inputs An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC. ... | 11/08/2011 |
| 8055962 | Testing IC functional and test circuitry having separate input/output pads Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test circuitry is electrically isolated from the functional circuitry and powe... | 11/08/2011 |
| 8055947 | Comparing supplied and sampled link ID bits on TMS lead An identification (ID) process comprises in each of a plurality of bit times, a debug test system asserting a control signal at a predefined state to a plurality of target systems, and each target system, having a bit pattern and the bit patterns being different amo... | 11/08/2011 |
| 8055231 | RF feedback engine coupled to receiver low noise amplifier Methods and apparatus to perform radio frequency (RF) analog-to-digital conversion are described. According to one example, a receiver includes an amplifier to amplify received analog RF signals and a mixer-free circuit for converting the received analog RF signals ... | 11/08/2011 |
| 8054861 | Primary, secondary, and tertiary codes synchronizing slots in a frame A method of processing data comprises the receiving a frame of data having a predetermined number of time slots (502,504,506). Each time slot comprises a respective plurality of data symbols (520). The method further comprises a primary (508), a... | 11/08/2011 |
| 8051351 | DDR circuit with addressable TAP linking circuitry and plural TAPS A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from th... | 11/01/2011 |
