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| Number | Title | Issue Date |
| 5091662 | High-speed low-power supply-independent TTL compatible input buffer A TTL compatible CMOS high-speed lower-power supply-independent input buffer has a first current mirror which supplies current to a reference node of the input buffer when the signal at the input node of the buffer goes to a high state. An MOS transistor ... | 02/25/1992 |
| 5089428 | Method for forming a germanium layer and a heterojunction bipolar transistor A method for preparing a germanium layer (22) adjacent to a germanium silicon layer (20). Initially, a P-germanium silicon layer (16) is deposited on to an N-germanium silicon layer (14). The continuous germanium layer (22) is formed by heating the layers... | 02/18/1992 |
| 5084874 | Enhanced test circuit A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs ... | 01/28/1992 |
| 5077591 | Electrostatic discharge protection for semiconductor input devices A method and structure for protecting an integrated circuit from electrostatic discharges are disclosed. A Shockley diode (22) is connected to an input bond pad (12) and to a MOSFET transistor (17) which is desired to be protected. The normally high break... | 12/31/1991 |
| 5074736 | Semiconductor wafer carrier design A carrier-susceptor for use in a continuous chemical vapor deposition reactor system serves as a carrier, cover and heat susceptor for a semiconductor wafer being processes through the reactor system.... | 12/24/1991 |
| 5073728 | Active load for ECL type outputs An active pull down circuit for a logic circuit, having a true and a complement output, a pull down transistor coupled to one of the true and complement outputs, a bias element for biasing the pull down transistor on, and a charge coupling element coupled... | 12/17/1991 |
| 5070261 | Apparatus and method for translating voltages An apparatus and method for translating voltages between logic levels is provided having an input section (11), a level shifter section (89) and an output section (137). Input section (11) provides two control voltages to the level shifter section (89) in... | 12/03/1991 |
| 5068599 | Integrated circuit having an enabling circuit for controlling primary and secondary subcircuits An integrated circuit (10) which includes primary circuit (12) and secondary circuit (17). An enabling circuit (16) allows package pins (15) to be shared between the primary circuit (12) and secondary circuit (17) responsive to voltages on the package pin... | 11/26/1991 |
| 5066872 | Speed-up technique for a constant di/dt buffer The disclosure relates to a circuit and method of reducing inductive voltage spikes caused by an abrupt change in current by an output transistor, by providing an input node for receiving an input voltage signal, providing an output node, providing a firs... | 11/19/1991 |
| 5065217 | Process for simultaneously fabricating isolation structures for bipolar and CMOS circuits An isolation structure for bipolar and CMOS circuits formed during the same processing steps to optimize the integration of bipolar and CMOS circuits. A deep trench (46) is formed in a semiconductor circuit for providing deep isolation for bipolar circuit... | 11/12/1991 |
| 5065043 | Biasing circuits for field effect transistors using GaAs FETS Hysteresis effects in low frequency field effect transistor circuits are minimized by using biasing or clamping circuits including field effect transistors.... | 11/12/1991 |
| 5065209 | Bipolar transistor fabrication utilizing CMOS techniques Disclosed is a bipolar transistor and a method of fabrication thereof compatible with MOSFET devices. A transistor intrinsic base region (54) is formed in the face of a semiconductor well (22), and covered with a gate oxide (44). The gate oxide (44) is op... | 11/12/1991 |
| 5059889 | Parametric measurement unit/device power supply for semiconductor test system Disclosed is a device power supply in a semiconductor test system for supplying programmed test pattern voltages to a semiconductor device under test and for current range switching of current range resistors without effecting the output voltage of the de... | 10/22/1991 |
| 5057443 | Method for fabricating a trench bipolar transistor A bipolar transistor formed in a trench depression such that a single impurity diffusing step is effective to form a buried collector layer electrically connected to a vertical collector conductor. The lateral diffusion forming the vertical collector cond... | 10/15/1991 |
| 5057461 | Method of mounting integrated circuit interconnect leads releasably on film A method and film/interconnect lead combination for attaching a plurality of sets of interconnect leads on a strip of film using an adhesive which loses bonding strength upon being exposed to energy such as heat or ultra violet light. The film holds the i... | 10/15/1991 |
| 5056094 | Delay fault testing method and apparatus A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs ... | 10/08/1991 |
| 5055888 | Zener diodes in a linear semiconductor device A Zener diode structure comprising a semiconductor substrate layer of a first conductivity type, a first epitaxially formed semiconductor layer of the first conductivity type disposed on the substrate layer, a second epitaxially formed semiconductor layer... | 10/08/1991 |
| 5056093 | System scan path architecture A system scan path architecture is provided by a device select module (DSM) (18) which may be used in conjunction with associated circuits (16a-b) to select secondary scan paths (PATH1-m) on each circuit for coupling with a primary scan path on a test bus... | 10/08/1991 |
| 5054024 | System scan path architecture with remote bus controller A system scan path architecture is provided by a device select module (DSM) (18) which may be used in conjunction with associated circuits (16a-b) to select secondary scan paths (PATHl-m) on each circuit for coupling with a primary scan path on a test bus... | 10/01/1991 |
| 5052886 | Semiconductor wafer orientation device A device having a circled array of tapered motor driven rollers center and find the flat edge of a semiconductor wafer by rotating the wafer until the flat edge is over a photo cell, at which time finder rollers secure the wafer in its centered and orient... | 10/01/1991 |
| 5051872 | Hemispherical non-glare illuminator A translucent hemispherical diffuser provides shadowless, uniform illumination of an object to be inspected or otherwise viewed. The optical medium of the translucent diffuser has a milk glass optical consistency, and/or one or more surfaces of the diffus... | 09/24/1991 |
| 5051612 | Prevention of parasitic mechanisms in junction isolated devices A method of preventing forward biasing of PN junctions in junction isolated semiconductor devices to prevent parasitic transistor action. A biasing element is connected to the substrate/isolation regions to switch the regions to a low potential. The metho... | 09/24/1991 |
| 5047973 | High speed numerical processor for performing a plurality of numeric functions Division and square root calculations are performed using an operand routing circuit (16) for receiving an operand N, and operand D and a seed value S and directing the operands and seed value to a multiplier (38). Single multiplier (38) is configured int... | 09/10/1991 |
| 5046363 | Apparatus for rapid non-destructive measurement of die attach quality in packaged integrated circuits A method and apparatus is disclosed for the non-destructive measurement of die-attach quality in packaged integrated circuit. The apparatus is used in a production line and uses acoustical pulses to generate signals from within the integrated circuit indi... | 09/10/1991 |
| 5047672 | ECL/TTL conversion circuit and translation programmable array logic A circuit (90) converts a true ECL signal to a true TTL signal. The circuit includes a differential circuit (180) that receives an ECL signal having high and low values. The differential circuit produces a differential signal therefrom that has a high val... | 09/10/1991 |
| 5044871 | Integrated circuit processing system A vacuum-tight wafer carrier, and a load lock suitable for use with this wafer carrier. The wafers are supported at each side by a slightly sloping shelf, so that minimal contact (line contact) is made between the wafer surface and the surface of the shel... | 09/03/1991 |
| 5046110 | Comparator error filtering for pattern inspector A laser pattern inspection and/or writing system which writes or inspects a pattern on a target on a stage, by raster scanning the target pixels. Inspection can also be done by substage illumination with non-laser light. A database, organized into frames ... | 09/03/1991 |
| 5043677 | Time reference signal generation system A reference time signal generation system 10 is provided which comprises a phase lock loop circuit 12 which generates a reference voltage Vm. The phase lock loop circuit 12 comprises first and second divider circuits 14 and 18 coupled to the in... | 08/27/1991 |
| 5042423 | Semiconductor wafer carrier design A carrier for use in a continuous chemical vapor deposition reactor system has a lid with tapered edges which match the sides of a recess in the carrier in which the lid resides during processing of the semiconductor to provide a precise fit for the lid a... | 08/27/1991 |
| 5041746 | Sense amplifier providing a rapid output transition A sense amplifier (38) uses a current source (40) to pull-up a product line (14) during as low-to-high transition. After a desired voltage is reached on the product line (14), the current source is turned off by a delay feedback circuit (44). A hold-up ci... | 08/20/1991 |
| 5040052 | Compact silicon module for high density integrated circuits A semiconductor module that densely packs integrated circuit chips to provide electronic systems or large memory modules in an array of stacked silicon boards. The semiconductor chips may be flip mounted and the back side of each chip is in thermal contac... | 08/13/1991 |
| 5037772 | Method for forming a polysilicon to polysilicon capacitor A first polysilicon layer (18) is initially deposited onto a layer of field oxide (16). A dielectric (26) is formed on a portion of the first polysilicon layer (18). A second polysilicon layer (28) is deposited over the dielectric (26) and the first polys... | 08/06/1991 |
| 5034337 | Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices A process of fabricating semiconductor devices involving plural epitaxial layer growth steps.... | 07/23/1991 |
| 5034635 | Positive to negative voltage translator circuit and method of operation There is disclosed a circuit and method for converting on/off logic signals from one medium to on/off signals useful in a different medium. The circuit is particularly adapted to translate from positive voltage levels to negative voltage levels. The circu... | 07/23/1991 |
| 5028878 | Dual memory timing system for VLSI test systems A timing system using shared address generator(s) to address memories that form the basis of each pin's timing reference generator can reduce the amount of hardware required to implement a "Timing Generator Per Pin" architecture in a VLSI tester by at lea... | 07/02/1991 |
| 5027014 | Translator circuit and method of operation There is disclosed a circuit and method for converting on/off logic signals from one medium to on/off signals useful in a different medium. The circuit is particularly adapted to translate from negative voltage levels to positive voltage levels. The circu... | 06/25/1991 |
| 5027132 | Position compensation of laser scan for stage movement A laser pattern inspection and/or writing system which writes or inspects a pattern on a target on a stage, by raster scanning the target pixels. Inspection can also be done by substage illumination with non-laser light. A database, organized into frames ... | 06/25/1991 |
| 5025205 | Reconfigurable architecture for logic test system A reconfigurable resource architecture enhances a test system's utilization by allowing product-mix dependent allocation of test system resources. The test system resources can be configured to test several device types with different pin counts simultane... | 06/18/1991 |
| 5024746 | Fixture and a method for plating contact bumps for integrated circuits This disclosure describes a plating fixture to hold a silicon wafer containing integrated circuits in a metal plating bath. The wafer is coated with photoresist to a thickness equal to the desired bump height and the desired bump locations patterened by s... | 06/18/1991 |
| 5023487 | ECL/TTL-CMOS translator bus interface architecture Described is an architecture for translating between ECL and TTL/CMOS signal levels in which the control signal applied to the translating circuitry is of the same type as the output signal of the device in which the architecture is used.... | 06/11/1991 |
