Did You Know...
...that the inventor of the electric motor was a blacksmith named Thomas Davenport? Described as "a brilliantly unsuccessful inventor", Davenport invented the first rotary electric motor. In 1836 he headed out -- on foot -- from his Vermont home to file a patent application at the Patent Office in Washington, D.C. By the time he got there, he had squandered away his money and couldn't afford the $30 filing fee so he turned around and went home. When he later mailed in his application with money he'd raised, the Patent office was destroyed in a fire. He did finally get credit for his invention on Feb. 5, 1837.
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| Number | Title | Issue Date |
| 8035156 | Split-gate non-volatile memory cell and method A method is disclosed for making a non-volatile memory cell on a semiconductor substrate. A select gate structure is formed over the substrate. The control gate structure has a sidewall. An epitaxial layer is formed on the substrate in a region adjacent to the sidew... | 10/11/2011 |
| 8030153 | High voltage TMOS semiconductor device with low gate charge structure and method of making A TMOS device (10) is formed using a semiconductor layer (16) of a first type. First and second regions (62,64) of the second type are formed in the semiconductor layer and are spaced apart. A third region (68) is formed in the semiconduc... | 10/04/2011 |
| 7919006 | Method of anti-stiction dimple formation under MEMS A method for making a MEMS structure comprises patterning recesses in a dielectric layer overlying a substrate, each recess being disposed between adjacent mesas of dielectric material. A conformal layer of semiconductor material is formed overlying the recesses and... | 04/05/2011 |
| 7904869 | Method of area compaction for integrated circuit layout design A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respec... | 03/08/2011 |
| 7858482 | Method of forming a semiconductor device using stress memorization A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then remo... | 12/28/2010 |
| 7793542 | Caddie-corner single proof mass XYZ MEMS transducer A three-axis MEMS transducer featuring a caddie-corner proof mass comprises a planar main body portion of conductive material and a planar extra mass caddie-corner feature. The main body portion includes a width, length, and at least four side edges. An x-axis sense... | 09/14/2010 |
| 7747889 | Bus having a dynamic timing bridge A data processing system may comprise an initiator device having an output whose timing is referenced by a clock input alone corresponding to a first delay along a signaling path. The exemplary data processing system further may further comprise a target device havi... | 06/29/2010 |
| 7736996 | Method for damage avoidance in transferring an ultra-thin layer of crystalline material with high crystalline quality A method for damage avoidance in transferring a monocrystalline, thin layer from a first substrate onto a second substrate involves epitaxial growth of a sandwich structure with a strained epitaxial layer buried below a monocrystalline thin layer, and lift-off and t... | 06/15/2010 |
| 7715227 | Programmable ROM using two bonded strata A read only memory implemented as a 3D integrated device has a first stratum, a second stratum, and bonded inter-strata connections for coupling the first stratum to the second stratum. The physical bonding between the two strata implements the programming of the re... | 05/11/2010 |
| 7704830 | Split gate memory cell using sidewall spacers A self-aligned split gate bitcell includes first and second regions of charge storage material separated by a gap devoid of charge storage material. Spacers are formed along sidewalls of sacrificial layer extending above and on opposite sides of the bitcell stack, w... | 04/27/2010 |
| 7653448 | NICAM processing method A NICAM processing method includes receiving and temporarily storing a current frame of A-channel and B-channel input data into a first memory at a first clock rate. Companded A-channel and B-channel data of a previous frame are read from a second memory at a second... | 01/26/2010 |
| 7645651 | LDMOS with channel stress A method of forming a metal oxide semiconductor (MOS) device comprises defining an active area in an unstrained semiconductor layer structure, depositing a hard mask overlying the active area and a region outside of the active area, patterning the hard mask to expos... | 01/12/2010 |
| 7592673 | ESD protection circuit with isolated diode element and method thereof An ESD protection circuit (20) includes an ESD device (24) and an isolation diode element (30). The ESD device includes a drain-source junction isolated ESD transistor (26,28). The isolation diode element is coupled in series with the ESD... | 09/22/2009 |
| 7592273 | Semiconductor device with hydrogen barrier and method therefor A method of forming a semiconductor device comprises providing a portion of a semiconductor device structure, wherein the portion includes a region susceptible to hydrogen incorporation due to subsequent device processing. For example, the subsequent device processi... | 09/22/2009 |
| 7589370 | RF power transistor with large periphery metal-insulator-silicon shunt capacitor An integrated MIS capacitor structure has a bottom electrode, a capacitor dielectric overlying the bottom electrode, and a plurality of capacitor top plates overlying the capacitor dielectric. In one form each capacitor top plate has a principal dimension and a less... | 09/15/2009 |
| 7581202 | Method for generation, placement, and routing of test structures in test chips A method of generating and placing of test structures in test chips comprises creating a control data set for one or more device types, generating a test structure layout in response to the control data set, and placing the test structure layout within a given pad a... | 08/25/2009 |
| 7522667 | Method and apparatus for dynamic determination of frames required to build a complete picture in an MPEG video stream A method for dynamically determining frames required to build a complete picture in an MPEG video stream includes decoding an order of frames in the MPEG video stream according to a dependency vector model. The dependency vector model is configured for determining a... | 04/21/2009 |
| 7508021 | RF power transistor device with high performance shunt capacitor and method thereof An integrated shunt capacitor comprises a bottom plate (86,88), a capacitor dielectric (92) overlying a portion of the bottom plate, a top plate (62) overlying the capacitor dielectric, a shield (74) overlying a portion of the top plate (... | 03/24/2009 |
| 7496364 | Media-independent handover (MIH) method featuring a simplified beacon A method for implementing a Media Independent Handover (MIH) service between one or more of a heterogeneous and a non-heterogeneous network comprises providing an MIH beacon from one or more of a network (Net) or a mobile node (MN); acknowledging a receipt of the MI... | 02/24/2009 |
| 7444012 | Method and apparatus for performing failure analysis with fluorescence inks A method for performing failure analysis on a semiconductor device under inspection includes preparing of a device sample using an encapsulation material containing a dye, the prepared device sample possibly including a failure area having wicked in encapsulation ma... | 10/28/2008 |
| 7442654 | Method of forming an oxide layer on a compound semiconductor structure A method of forming a dielectric layer structure on a supporting semiconductor structure having a first surface comprises providing a first beam of oxide; depositing a first layer of oxide on the first surface of the supporting semiconductor structure using the firs... | 10/28/2008 |
| 7441102 | Integrated circuit with functional state configurable memory and method of configuring functional states of the integrated circuit memory An integrated circuit comprises a processor configured for fetching and executing opcodes, a system bus, and a memory coupled to the processor via the system bus. The memory includes logic circuitry for detecting functional states of the memory, wherein the memory (... | 10/21/2008 |
| 7439584 | Structure and method for RESURF LDMOSFET with a current diverter Methods and apparatus are provided for reducing substrate leakage current of RESURF LDMOSFET devices. A semiconductor device comprises a semiconductor substrate (22) of a first type; first and second terminals (39,63) laterally spaced-apart on a surfac... | 10/21/2008 |
| 7432565 | III-V compound semiconductor heterostructure MOSFET device A III-V based, implant free MOS heterostructure field-effect transistor device comprises a gate insulator layer overlying a compound semiconductor substrate; ohmic contacts coupled to the compound semiconductor substrate proximate opposite sides of an active device ... | 10/07/2008 |
| 7429506 | Process of making a III-V compound semiconductor heterostructure MOSFET A method of forming a compound semiconductor device comprises forming a gate insulator layer overlying a compound semiconductor substrate, defining an active device region within the compound semiconductor substrate, forming ohmic contacts to the compound semiconduc... | 09/30/2008 |
| 7403624 | BTSC encoder and integrated circuit A BTSC encoder includes dual channel ADC, sync separator, audio processor, filtering device, and a composite audio signal generating device. The filtering device includes a first filter for providing a filtered L+R signal, and a second filter for providing at least ... | 07/22/2008 |
| 7402477 | Method of making a multiple crystal orientation semiconductor device A method of having transistors formed in enhanced performance crystal orientations begins with a wafer having a semiconductor substrate (12,52) of a first surface orientation, a thin etch stop layer (14,54) on the semiconductor substrate, a buried oxid... | 07/22/2008 |
| 7386821 | Primitive cell method for front end physical design A method for forming an integrated circuit (280) comprises accessing (282) a library of primitive cells and edge codes in the formation of an integrated circuit layout. At least one edge code of at least one previously placed primitive cell (284... | 06/10/2008 |
| 7373539 | Parallel path alignment method and apparatus A method for aligning parallel path data bit streams that may contain skewed data between bit streams and an integrated circuit are disclosed. The method includes, for each bit stream, sampling P data presented on a positive edge of a clock, sampling N data presente... | 05/13/2008 |
| 7365587 | Contention-free keeper circuit and a method for contention elimination A contention-free keeper circuit including a keeper circuit having a first node and a second node, is provided. The contention-free keeper circuit may further include a delay element for providing time delay. The contention-free keeper circuit may further include a ... | 04/29/2008 |
| 7358743 | Accumulated current counter and method thereof An accumulated current counter (11) includes a sense resistor (30) configured for being coupled in series between an electronic circuit (13) and a power source (12). The sense resistor is further for use in sensing a voltage (VIN(i) | 04/15/2008 |
| 7309628 | Method of forming a semiconductor device A semiconductor device is formed as part of an integrated circuit. The semiconductor device, which is formed in an active semiconductor layer, is surrounded by a guardian that provides a diffusion barrier against contaminants and also provides assistance in avoiding... | 12/18/2007 |
| 7296248 | Method and apparatus for compiling a parameterized cell A method of generating a parameterized cell is disclosed herein. The method comprises performing a compiling interpretation on a structure layout. The compiling interpretation includes i) determining and analyzing shape relationships of the structure layout, and ii)... | 11/13/2007 |
| 7293153 | Method and system for direct access to a non-memory mapped device memory A processing system that interacts with external devices has a processor, a memory, and a controller. The memory stores templates that provide access protocol information about the external devices. When an external device is to be accessed, the operating system, wh... | 11/06/2007 |
| 7286070 | RF carrier generator and method thereof An RF carrier generator comprises a circuit for sequentially counting as a function of a randomized offset and time interval, and a memory coupled to the sequential counting circuit. The memory stores samples of a desired Sigma-Delta modulator sequence bit stream. R... | 10/23/2007 |
| 7284231 | Layout modification using multilayer-based constraints A method for improving manufacturability of a design includes performing space or enclosure checks on multiple interacting layers of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design databas... | 10/16/2007 |
| 7276406 | Transistor structure with dual trench for optimized stress effect and method therefor A method for forming a portion of a semiconductor device structure comprises providing a semiconductor-on-insulator substrate having a semiconductor active layer, an insulation layer, and a semiconductor substrate. A first isolation trench is formed within the semic... | 10/02/2007 |
| 7215150 | Method and circuit for maintaining I/O pad characteristics across different I/O supply voltages A circuit implements a method to adjust input/output (I/O) characteristics of an I/O pad circuit (10) depending upon which value of an I/O supply voltage is used within a range of supply voltages. An I/O supply voltage being supplied to the pad circuit is det... | 05/08/2007 |
| 7169654 | Method of forming a semiconductor device A method of integrating a non-MOS transistor device and a CMOS electronic device on a semiconductor substrate includes forming openings within an active semiconductor layer in first and second regions of a semiconductor substrate. The first region corresponds to a n... | 01/30/2007 |
| 7170135 | Arrangement and method for ESD protection An arrangement (200) and method for scalable ESD protection of a semiconductor structure (140), a protection structure (120) providing a discharge transistor (110) path from an input/output node (130) to ground or another node if a... | 01/30/2007 |
