Quotables
"During my service in the United States Congress, I took the initiative in creating the Internet."
Al Gore ; The basis for the later misquote by US Republicans that Gore had "invented" the Internet. Gore was the leading political champion of the modern-day Internet.
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| Number | Title | Issue Date |
| 8180931 | USB-attached-SCSI flash-memory system with additional command, status, and control pipes to a smart-storage switch An electronic flash-memory card has additional pipes for commands and status messages so that data pipes are not clogged with commands and status messages, allowing for a higher data throughput. The command and status pipes are activated when a UAS/BOT detector dete... | 05/15/2012 |
| 8179455 | Optical black-level cancellation for optical sensors using open-loop sample calibration amplifier A Optical Black Pixel (OBP) cancellation circuit corrects offsets in sensors in a CCD/CMOS image sensor when reading dark pixels such at the periphery. A pixel voltage is switched to a sampling capacitor during two phases of the same pixel pulse. Sampling capacitors... | 05/15/2012 |
| 8176238 | Command queuing smart storage transfer manager for striping data to raw-NAND flash modules A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA... | 05/08/2012 |
| 8171204 | Intelligent solid-state non-volatile memory device (NVMD) system with multi-level caching of multiple channels A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed ... | 05/01/2012 |
| 8166221 | Low-power USB superspeed device with 8-bit payload and 9-bit frame NRZI encoding for replacing 8/10-bit encoding A Low-power flash-memory device uses a modified Universal-Serial-Bus (USB) 3.0 Protocol to reduce power consumption. The bit clock is slowed to reduce power and the need for pre-emphasis when USB cable lengths are short in applications. Data efficiency is improved b... | 04/24/2012 |
| 8140719 | Dis-aggregated and distributed data-center architecture using a direct interconnect fabric A data center has several dis-aggregated data clusters that connect to the Internet through a firewall and load-balancer. Each dis-aggregated data cluster has several dis-aggregated compute/switch/disk chassis that are connected together by a mesh of Ethernet links.... | 03/20/2012 |
| 8108590 | Multi-operation write aggregator using a page buffer and a scratch flash block in each of multiple channels of a large array of flash memory to reduce block wear A flash system has multiple channels of flash memory chips that can be accessed in parallel. Host data is assigned to one of the channels by a multi-channel controller processor and accumulated in a multi-channel page buffer. When a page boundary in the page buffer ... | 01/31/2012 |
| 8099651 | Subsystem and method for encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use in a 76-bit memory module A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are con... | 01/17/2012 |
| 8098733 | Multi-directional motion estimation using parallel processors and pre-computed search-strategy offset tables A motion estimator uses many parallel Arithmetic-Logic-Unit (ALU) processors to simultaneously perform searches in many directions from a starting point. Each processor follows a different path outward from the starting point, generating sum-of-absolute differences ... | 01/17/2012 |
| 8072721 | ESD protection using a capacitivly-coupled clamp for protecting low-voltage core transistors from high-voltage outputs An electro-static-discharge (ESD) protection circuit protects core transistors. An internal node to the gate of an n-channel output transistor connects to the drain of an n-channel gate-grounding transistor to ground. The gate of the gate-grounding transistor is a c... | 12/06/2011 |
| 8037234 | Command queuing smart storage transfer manager for striping data to raw-NAND flash modules A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA... | 10/11/2011 |
| 8035408 | Socket fixture for testing warped memory modules on a PC motherboard A memory module test socket can accept modules with bent or warped printed-circuit boards (PCBs). A support plate is mounted above a Personal Computer (PC) motherboard by standoffs. An extender card fits through a slot in the support plate. The bottom edge of the ex... | 10/11/2011 |
| 8022721 | Conveyor-based memory-module tester with elevators distributing moving test motherboards among parallel conveyors for testing A conveyor-stack test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. A loader-unloader removes tested memory modules from test sockets on the motherboards and inser... | 09/20/2011 |
| 8022720 | Parking structure memory-module tester that moves test motherboards along a highway for remote loading/unloading A parking-structure test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. An unloader removes tested memory modules from test sockets on the motherboards, and a loade... | 09/20/2011 |
| 7999512 | Single-power-transistor battery-charging circuit using voltage-boosted clock A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between th... | 08/16/2011 |
| 7994455 | Control circuit for fast heating of a positive-temperature-coefficient heating component Traditional temperature-control products have the problem that the temperature of the working surface reaches the setting temperature too slowly when heating up or recovering from a temperature drop. A traditional temperature control circuit and temperature-settings... | 08/09/2011 |
| 7966462 | Multi-channel flash module with plane-interleaved sequential ECC writes and background recycling to restricted-write flash chips A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter... | 06/21/2011 |
| 7966429 | Peripheral devices using phase-change memory Peripheral devices store data in non-volatile phase-change memory (PCM). PCM cells have alloy resistors with high-resistance amorphous states and low-resistance crystalline states. The peripheral device can be a Serial AT-Attachment (SATA) or integrated device elect... | 06/21/2011 |
| 7965546 | Synchronous page-mode phase-change memory with ECC and RAM cache Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on t... | 06/21/2011 |
| 7960992 | Conveyor-based memory-module tester with elevators distributing moving test motherboards among parallel conveyors for testing A conveyor-stack test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. A loader-unloader removes tested memory modules from test sockets on the motherboards and inser... | 06/14/2011 |
| 7948224 | Feedback controller having multiple feedback paths A feedback controller comprises first and second feedback circuits. The first feedback circuit is connected between an input node and an output node and has an error node. The first feedback circuit comprising a feedback amplifier for comparing a feedback signal to ... | 05/24/2011 |
| 7934074 | Flash module with plane-interleaved sequential writes to restricted-write flash chips A flash memory controller on a PCIE bus controls flash-memory modules on a flash bus. The flash-memory modules are plane-interleaved using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB an... | 04/26/2011 |
| 7930531 | Multi-partition USB device that re-boots a PC to an alternate operating system for virus recovery A multi-partition Universal Serial Bus (USB) device has a flash memory with multiple partitions of storage. Some partitions are for different operating systems and store OS images. Another partition has a control program while a user partition stores user data and u... | 04/19/2011 |
| 7921088 | Logical operations encoded by a function table for compressing index bits in multi-level compressed look-up tables Compressed stride tables in a multi-bit Trie structure perform lookups. An input lookup key is divided into strides including a current stride of S bits. A valid entry in a current stride table is located by compressing the S bits, forming a compressed index of D bi... | 04/05/2011 |
| 7917327 | Chip handler with a buffer traveling between roaming areas for two non-colliding robotic arms Two robotic arms roam in separate, non-overlapping areas of a test station, avoiding collisions. A traveling buffer moves along x-tracks between a front position and a back position. In the front position, a first robotic arm loads IC chips from an input tray or sta... | 03/29/2011 |
| 7904655 | Branching memory-bus module with multiple downlink ports to standard fully-buffered memory modules A branching memory-bus module has one uplink port and two or more downlink ports. Frames sent downstream by a host processor are received on the uplink port and repeated to the multiple downlink ports to two or more branches of memory modules. Frames sent upstream t... | 03/08/2011 |
| 7889544 | High-speed controller for phase-change memory peripheral device Peripheral devices store data in non-volatile phase-change memory (PCM). PCM cells have alloy resistors with high-resistance amorphous states and low-resistance crystalline states. The peripheral device can be a Multi-Media Card/Secure Digital (MMC/SD) card. A PCM c... | 02/15/2011 |
| 7884631 | Parking structure memory-module tester that moves test motherboards along a highway for remote loading/unloading A parking-structure test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. An unloader removes tested memory modules from test sockets on the motherboards, and a loade... | 02/08/2011 |
| 7865630 | Single-chip multi-media card/secure digital (MMC/SD) controller reading power-on boot code from integrated flash memory for user storage A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/... | 01/04/2011 |
| 7861312 | MP3 player with digital rights management A portable media player receives encrypted audio files and an encrypted content key from a central license server on the Internet. The media player supports digital rights management (DRM) by storing the encrypted audio file in its flash memory and disabling copying... | 12/28/2010 |
| 7859883 | Recordable electrical memory A memory device includes a plurality of memory cells each including a recordable layer between two metal layers, the recordable layer including a first sub-cell and a second sub-cell. Each memory cell is constructed and designed to change from an as-deposited state ... | 12/28/2010 |
| 7855099 | Manufacturing method for a secure-digital (SD) flash card with slanted asymmetric circuit board A flash-memory device has a printed-circuit board assembly (PCBA) with a PCB with a flash-memory chip and a controller chip. The controller chip includes an input/output interface circuit to an external computer over a Secure-Digital (SD) interface, and a processing... | 12/21/2010 |
| 7827218 | Deterministic lookup using hashed key in a multi-stride compressed trie structure An input lookup key is hashed and the hashed key divided into stride bits into a multi-level Trie structure. A compression function logically combines the stride bits to generate the compressed index bits into the stride tables. The bucket in the last stride table f... | 11/02/2010 |
| 7826214 | Heat exchange enhancement A heat exchange structure includes elongated air ducts. Each air duct has a first opening and a second opening at two ends of the air duct to allow air to enter and exit the air duct, respectively. The heat exchange structure includes an exterior heat exchange surfa... | 11/02/2010 |
| 7814337 | Secure flash-memory card reader with host-encrypted data on a flash-controller-mastered bus parallel to a local CPU bus carrying encrypted hashed password and user ID A secure flash-card reader reads a user ID from a secure card and finds a matching entry with a hashed password in a user table on the reader. An encrypted key is received from a secure host that hashes and encrypts a password the user types into the host and the us... | 10/12/2010 |
| 7813158 | Recordable electrical memory A memory device includes memory cells each having a recordable layer between two metal layers, each memory cell being constructed and designed to change from a first state to a second state upon application of an initialization signal, and change from the second sta... | 10/12/2010 |
| 7812757 | Hybrid analog-to-digital converter (ADC) with binary-weighted-capacitor sampling array and a sub-sampling charge-redistributing array for sub-voltage generation A hybrid Analog-to-Digital Converter (ADC) has a binary-weighted capacitor array and a sub-voltage capacitor array that are coupled together by a coupling capacitor. The sub-voltage capacitor array uses a minimum capacitor size that matches the minimum capacitor siz... | 10/12/2010 |
| 7811880 | Fabrication of recordable electrical memory A memory cell of a memory device is fabricated by forming a first electrode on a substrate, positioning a photo mask at a first position relative to the substrate, and forming a first material layer on the first electrode based on a pattern on the photo mask. The ph... | 10/12/2010 |
| 7809862 | Dual-mode switch for multi-media card/secure digital (MMC/SD) controller reading power-on boot code from integrated flash memory for user storage A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/... | 10/05/2010 |
| 7808282 | Out-of-band signaling using detector with equalizer, multiplier and comparator Power-down mode is activated when equal voltages are detected on a pair of differential inputs. The voltage difference across the differential inputs is equalized by an equalizer and then applied to a multiplier and smoothed and filtered by a low-pass filter to prod... | 10/05/2010 |
