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| Number | Title | Issue Date |
| 5765207 | Recursive hardware state machine A state machine computing system provides multiple state registers, a recursive hardware state machine computing system; particularly address translation hardware which can be used in multiprocessors, parallel machines and massively parallel machines. The... | 06/09/1998 |
| 5754810 | Specialized millicode instruction for certain decimal operations A millicode method for packing the hexadecimal digits from a plurality of bytes in each of two millicode registers (R1,R1) into one of the two millicode registers extracts the rightmost hexadecimal digit from each of a plurality of bytes stored in millico... | 05/19/1998 |
| 5745386 | Timing diagram method for inputting logic design parameters to build a testcase for the logic diagram A. system (i.e. a tool set) provides logic verification at the logic design level in which an external stimulus to the design is derived from a series of generalized timing diagrams that obey the interface protocols of the logic design under test. A timin... | 04/28/1998 |
| 5732234 | System for obtaining parallel execution of existing instructions in a particulr data processing configuration by compounding rules based on instruction categories A system for processing a sequence of instructions has a set of compounding rules based on an analysis of existing instructions to separate them into different classes. The analysis determines which instructions qualify, either with instructions in their ... | 03/24/1998 |
| 5713035 | Linking program access register number with millicode operand access In a milli-mode processor, bits (0-6) of an access list entry token (ALET) in the program access register must be zeros in order for access register translation to be successful. When the ALET is being copied from a program access register to a millicode ... | 01/27/1998 |
| 5704055 | Dynamic Reconfiguration of main storage and expanded storage by means of a service call logical processor A data processing system has a processing unit and a memory which provides a common pool of physical storage. This storage is initially assigned as either main storage or expanded storage during power on. Subsequent to the initial assignment, storage assi... | 12/30/1997 |
| 5701430 | Cross-cache-line compounding algorithm for scism processors A certain class of computer has been previously described which has improved performance through the analysis of instructions comprising the computer's control program and appending control information to the instructions in the form of tags. One such com... | 12/23/1997 |
| 5694617 | System for prioritizing quiesce requests and recovering from a quiescent state in a multiprocessing system with a milli-mode operation A milli-mode routine handles a quiesce interrupt, and causes all the processors in the system to enter a quiesced state. A single bit of a millicode control register indicates a quiesced state and drives an output of the processor to indicate the processo... | 12/02/1997 |
| 5694612 | Self-timed interface for a network of computer processors interconnected in parallel A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of t... | 12/02/1997 |
| 5694587 | Specialized millicode instructions for test PSW validity, load with access test, and character translation assist A pipelined computer processor in a milli-mode architected state tests the validity of a program status word with a mask stored in a millicode general register. The mask indicates bits in the program status word which are to be zeros if the word is valid.... | 12/02/1997 |
| 5680598 | Millicode extended memory addressing using operand access control register to control extended address concatenation A millicode instruction loads a millicode address extension register with extended address bits, and an operand access control register that signals when a logical address is to be extended by the extra bits, and when it should be treated as only a 31 bit... | 10/21/1997 |
| 5673391 | Hardware retry trap for millicoded processor Retry trap in the processor system detects the occurrence of a hardware retry during a millicode routine. In operation, millicode resets the retry trap to "O" at the start of a millicode sequence that is sensitive to a retry operation being at some stage ... | 09/30/1997 |
| 5652853 | Multi-zone relocation facility computer memory system A memory reconfiguration system now allows a guest's absolute storage space to be mapped to multiple discontiguous host absolute storage space. A multi-zone relocation facility is provided for relocating multiple zones of the memory of the computer system... | 07/29/1997 |
| 5651033 | Inter-system data communication channel comprised of parallel electrical conductors that simulates the performance of a bit serial optical communications link A self-timed interface (STI) links two physically separated systems or nodes. A transmit state machine forms each word in a serial bit stream into a plurality of bytes and generates idle and data character sequences. Each byte is separately encoded in a r... | 07/22/1997 |
| 5639163 | On-chip temperature sensing system A pair of on-chip thermal sensing diodes are formed together and interconnected with a common cathode to form a differential sensing pair. A pair of precision resistors external to the chip generates two constant currents, one for each diode, with a ratio... | 06/17/1997 |
| 5633877 | Programmable built-in self test method and controller for arrays An array built-in self test system has a scannable memory elements and a controller which, in combination, allow self test functions (e.g. test patterns, read/write access, and test sequences) to be modified without hardware changes to the test logic. Tes... | 05/27/1997 |
| 5625808 | Read only store as part of cache store for storing frequently used millicode instructions A read only storage (ROS) array holds a small set of relatively simple millicode instructions; those millicode instruction routines which are most commonly called on in executing common application workloads. The millicode read only store is implemented a... | 04/29/1997 |
| 5621909 | Specialized millicode instruction for range checking A range check instruction sequence, which performs a logical comparison between two 32-bit values and updates the condition code as a result. It operates identically to the ESA/390 instruction compare logical (CLR) except for the way in which the conditio... | 04/15/1997 |
| 5613068 | Method for transferring data between processors on a network by establishing an address space for each processor in each other processor's A multi-system interconnect facility in which each central processor complex in the system has an assigned storage space for each other central processor complex in the system for use in communicating with each other central processor complex. The allegia... | 03/18/1997 |
| 5611062 | Specialized millicode instruction for string operations Special millicode instructions accelerate the "inner loop" portion of a millicode routine to execute ESA/390 string instructions. Specifically, these millicode instructions are: Replicate Byte, Find Byte Equal, Find Byte Not Equal, Compare String Bytes in... | 03/11/1997 |
| 5598442 | Self-timed parallel inter-system data communication channel A self-timed interface (STI) links two physically separated systems or nodes. A transmit state machine forms each word in a serial bit stream into a plurality of bytes and generates idle and data character sequences. Each byte is separately encoded in a r... | 01/28/1997 |
| 5584042 | Dynamic I/O data address relocation facility For parallel, massively parallel and data server networks a zone relocation facility and dynamic I/O data address relocation facility which allows the relocation of memory space for partitions for on or more clients or guests while the client guest and on... | 12/10/1996 |
| 5577078 | Edge detector An edge detector has a digital phase locking loop in which one of the signals (e.g., the data signal) is coupled to a delay chain that develops a series of incrementally phase delayed versions of the input. Adjacent phase delayed pairs are selected, one p... | 11/19/1996 |
| 5574938 | Allowed operational-link transceiver table verifies the operational status of transceivers in a multiple conductor data transmission link A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to tr... | 11/12/1996 |
| 5568526 | Self timed interface A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase ali... | 10/22/1996 |
| 5568075 | Timing signal generator A programmable, timing signal generator propagates a digital wave along a delay chain comprised of series connected inverters that has sufficient stages that the edge of the wave will not propagate to the end during one system clock cycle time. The delay ... | 10/22/1996 |
| 5561758 | Tunnel icon A process icon based on a tunnel concept in which the icon has an input and an output portal through which an object is dragged in order to invoke the process. The direction of the process invoked (e.g., encrypt to decrypt or decrypt to encrypt) can be de... | 10/01/1996 |
| 5554946 | Timing signal generator A programmable, timing signal generator propagates a digital wave along a delay chain comprised of series connected inverters that has sufficient stages that the edge of the wave will not propagate to the end during one system clock cycle time. The delay ... | 09/10/1996 |
| 5522088 | Shared channel subsystem has a self timed interface using a received clock signal to individually phase align bits received from a parallel bus A shared channel subsystem has an input-output element for coupling each of a plurality of input-output controllers to each of a plurality of processor nodes by means of a self-timed interface (STI) in which a clock signal clocks bit serial data onto a pa... | 05/28/1996 |
| 5513377 | Input-output element has self timed interface using a received clock signal to individually phase aligned bits received from a parallel bus An enhanced input-output element has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line... | 04/30/1996 |
| 5502826 | System and method for obtaining parallel existing instructions in a particular data processing configuration by compounding instructions Scalable compound instruction set machine and method which provides for processing a set of instructions or program to be executed by a computer to determine statically which instructions may be combined into compound instructions which are executed in pa... | 03/26/1996 |
| 5488707 | Apparatus for predicting overlapped storage operands for move character An apparatus is presented and proved for detecting storage operand overlap for instructions having identical overlap detection requirements as the move character (MVC) instruction. The apparatus is applicable to all Enterprise Systems Architecture (ESA)/3... | 01/30/1996 |
| 5481738 | Apparatus and method for communicating a quiesce and unquiesce state between elements of a data processing complex A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to tr... | 01/02/1996 |
| 5475853 | Cache store of instruction pairs with tags to indicate parallel execution A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer sys... | 12/12/1995 |
| 5471628 | Multi-function permutation switch for rotating and manipulating an order of bits of an input data byte in either cyclic or non-cyclic mode In a digital computer system both rotation of bits in a data byte and rotation in combination with additional manipulation, a multifunction permutation switch, in a cyclic mode of operation, connects the input bit lines to the output bit lines so that the... | 11/28/1995 |
| 5465377 | Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer sys... | 11/07/1995 |
| 5459844 | Predecode instruction compounding A digital computer system capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions includes an instruction compounding unit for analyzing the instr... | 10/17/1995 |
| 5450073 | Controlling power sequencing of a control unit in an input/output system A mechanism for controlling the powering-on and powering-off of control units in a data processing system having a plurality of channels, a plurality of control units, and a communications network of links for linking the channels to the control units. Ea... | 09/12/1995 |
| 5448746 | System for comounding instructions in a byte stream prior to fetching and identifying the instructions for execution A system with an apparatus that can be used in the compounding of instructions for CISC architectures and architectures with other attributes, including RISC. The compounding is performed before instruction execution and it results in a compound instructi... | 09/05/1995 |
| 5446850 | Cross-cache-line compounding algorithm for scism processors A system for compounding instructions across cache line boundaries transfers an instruction line from a relatively slow memory to a instruction compounding unit if there is a miss for an instruction in that line in the instruction cache. At the same time ... | 08/29/1995 |
