Bizarre Patents
Wearable Device For Feeding and Observing Birds and Other Flying Animals
A device for feeding and observing flying animals comprising a hat, a support mounted on the hat and extending outward from the hat, and a feeder mounted on the support.
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| Number | Title | Issue Date |
| 8010925 | Method and system for placement of electric circuit components in integrated circuit design The invention relates to a method and a system for placing electric circuits in integrated circuit chip design. Specifically, the invention encompasses performing a global placement step placing the cells into bins on the chip, as well as a detailed placement proces... | 08/30/2011 |
| 7987086 | Software entity for the creation of a hybrid cycle simulation model Disclosed is a software entity for constructing a Hybrid Cycle Simulation model comprising Compiled Data Units (CDUs) for use in design verification. The simulation model may contain a plurality of 1-cycle CDUs, optimized for simulation throughput, and 2-cycle CDUs,... | 07/26/2011 |
| 7917777 | System for circulating power usage information on a closed ring communication path with multi-node computer system A method of regulating power for multi-node computer system components has a closed-ring path that links all the power governors and circulating in the ring is a system power number that represents the power consumption of the entire system. Meanwhile, all the gover... | 03/29/2011 |
| 7840857 | Method and system for automated handling of resolvable and non-resolvable errors in execution of system management flows consisting of system management tasks The present invention provides a method and system for automated handling of resolvable and non-resolvable errors in the execution of system management flows by enhancing Workflow Engines (30) by an Error Handling component (40) and by adding a support... | 11/23/2010 |
| 7809874 | Method for resource sharing in a multiple pipeline environment Disclosed is a method and apparatus for arbitration between multiple pipelines over shared resources for an SMP computer system. The computer includes logic to defer arbitration until later in the pipeline to help reduce latency to each pipeline. Also, introduced is... | 10/05/2010 |
| 7739545 | System and method to support use of bus spare wires in connection modules In a computer system with multiple chips connected via a connection module with high speed elastic interface buses that support bus repair is enhanced by use of a spare net. Support is provided to ensure that the spare net can be tested in the same way that every no... | 06/15/2010 |
| 7739526 | System for regulating system power by controlling memory usage based on an overall system power measurement A method for regulating system power using a power governor for DRAM in a multi-node computer system regulating memory power consumption of an entire computer system employs a closed ring that connects all the power governors within the system to enable them to work... | 06/15/2010 |
| 7702972 | Method and apparatus for SRAM macro sparing in computer chips SRAM macro sparing allows for full chip function despite the loss of one or more SRAM macros. The controls and data flow for any single macro within a protected group are made available to the spare or spares for that group. This allows a defective or failed SRAM ma... | 04/20/2010 |
| 7692480 | System to evaluate a voltage in a charge pump and associated methods A system to evaluate a voltage in a charge pump may include a transistor, and a transistor drain carried by the transistor with the transistor drain receiving a reference current. The system may also include a transistor gate carried by the transistor and connected ... | 04/06/2010 |
| 7676779 | Logic block timing estimation using conesize A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based ... | 03/09/2010 |
| 7650693 | Method of assembling electronic components of an electronic system, and system thus obtained An electronic system comprising: an electronic system support substrate for the attachment of components of the electronic system, the electronic system support substrate including electric signal propagation paths for the propagation of electric signals between the... | 01/26/2010 |
| 7650535 | Array delete mechanisms for shipping a microprocessor with defective arrays Detecting and correcting errors in arrays after ABIST testing, after ABIST testing, detected errors are faults are isolated by blowing a fuse. ... | 01/19/2010 |
| 7646724 | Dynamic blocking in a shared host-network interface A method, system, and program product for a data processing system having multiple hosts which dynamically determines blocking of packets in the data processing system. A connection is established between a host and an adapter for communication with a Local Area Net... | 01/12/2010 |
| 7636262 | Synchronous memory having shared CRC and strobe pin A memory system having a memory element chip (DRAM) and a memory controller chips having a plurality of drivers and receivers and latches for transferred data. For writes clocks, write data and write for CRC (cyclic redundancy checks) is transferred to the DRAM from... | 12/22/2009 |
| 7634708 | Relocatable storage protect keys for system main memory Storage protection keys and system data share the same physical storage. The key region is dynamically relocatable by firmware. A Configuration Array is used to map the absolute address of the key region in to its physical address. The absolute address of keys can b... | 12/15/2009 |
| 7590899 | Processor memory array having memory macros for relocatable store protect keys A DDR SDRAM DIMM for a mainframe main storage subsystem has a plurality of DDR SDRAMs on a rectangular printed circuit board having a first side and a second side, a length (152 MM=6 inch) between 149 and 153 millimeters and optimized at 149.15 mm or 151.35 mm in le... | 09/15/2009 |
| 7577795 | Disowning cache entries on aging out of the entry Portions of data in a processor system are stored in a slower main memory and are transferred to a faster memory comprising a hierarchy of cache structures between one or more processors and the main memory. For a system with shared L2 cache(s) between the processor... | 08/18/2009 |
| 7574548 | Dynamic data transfer control method and apparatus for shared SMP computer systems As a performance critical (high or full speed) request for a computer system data bus travels down a central pipeline, the system detects whether the interface data bus is currently empty or there is an ongoing half-speed transfer. If there is an ongoing low speed t... | 08/11/2009 |
| 7565636 | System for performing verification of logic circuits The present invention relates to a system for verifying the proper operation of a digital logic circuit and program product therefore. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed t... | 07/21/2009 |
| 7559002 | Multi-thread parallel segment scan simulation of chip element performance A microprocessor simulation method, system, and program product, which are built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring dat... | 07/07/2009 |
| 7546565 | Method for comparing two designs of electronic circuits A method implemented as a computer program product for comparing two designs of electronic circuits, wherein the design representations comprise several hierarchically related sheets. The method comprises the steps of (a) identifying corresponding top-sheets of the ... | 06/09/2009 |
| 7536613 | BIST address generation architecture for multi-port memories Disclosed is testing multi-port array macros where latches and logic are used to control the relationship between the write and read port of the array. This makes allowance for many different configurations of reading and writing the array. This also allows for grea... | 05/19/2009 |
| 7530038 | Method and placement tool for designing the layout of an electronic circuit According to the present invention a method for the placement of electronic circuit components is provided that supports design modifications by realizing and maintaining relations between the layouts of the components (i1 to i6). These relations are b... | 05/05/2009 |
| 7529997 | Method for self-correcting cache using line delete, data logging, and fuse repair correction An apparatus and method for protecting a computer system from array reliability failures uses Array Built-In Self-Test logic along with code and hardware to delete cache lines or sets that are defective, identify corresponding fuse repair values, proactively call ho... | 05/05/2009 |
| 7523267 | Method for ensuring fairness among requests within a multi-node computer system A method to use of dual valid bit sets including a regular bit set and alternate valid bits set which prevents new requests to a given cache line from entering a multi-nodal computer systems' nest system until all requests to the given cache line have been completed... | 04/21/2009 |
| 7509552 | Multi-thread parallel segment scan simulation of chip element performance A microprocessor simulation method, which is built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring data at an initial time. The hard... | 03/24/2009 |
| 7506287 | Method, system, and program product for pre-compile processing of hardware design language (HDL) source files A method includes pre-compilation operations on HDL source code files, creating a “make it” file, on demand processing of the HDL source code in an HDL source browser, and resolving overloaded function and operator calls in an HDL source code browser debugger. C... | 03/17/2009 |
| 7505284 | System for assembling electronic components of an electronic system An electronic system comprising: an electronic system support substrate for the attachment of components of the electronic system, the electronic system support substrate including electric signal propagation paths for the propagation of electric signals between the... | 03/17/2009 |
| 7496866 | Method for optimizing of pipeline structure placement Using a computer and storage, a circuit design process is executed to preserve overall design quality while obtaining quality placements for a full class of pipeline structure signatures. These signatures include classic latch to latch pipelines, as well as a variet... | 02/24/2009 |
| 7490310 | Method for creating a layout for an electronic circuit The present invention relates to creating a layout of an electronic circuit from a netlist of interconnected components, wherein the components can be represented by planar geometric shapes in the layout. The advantages of the present invention are achieved by tight... | 02/10/2009 |
| 7483825 | Method for the creation of a hybrid cycle simulation model Disclosed is a method for constructing a Hybrid Cycle Simulation model comprising Compiled Data Units (CDUs) for use in design verification. The simulation model may contain a plurality of 1-cycle CDUs, optimized for simulation throughput, and 2-cycle CDUs, optimize... | 01/27/2009 |
| 7484043 | Multiprocessor system with dynamic cache coherency regions A multiprocessor computer system has a plurality of processing nodes which use processor state information to determine which coherent caches in the system are required to examine a coherency transaction produced by a single originating processor's storage request. ... | 01/27/2009 |
| 7484023 | Computer system apparatus for stabilizing asynchronous interfaces A computer system apparatus for asynchronous data transfer between a source and sink without the use of an asynchronous control signal. includes metastability circuits, data change detection logic, a stability window delay counter, and a mux/register pair to allow f... | 01/27/2009 |
| 7480886 | VLSI timing optimization with interleaved buffer insertion and wire sizing stages The invention relates to layout of circuit components, including determining the interconnections, buffers, or path nets between circuit blocks or circuit components and input/output bonding pads. This is accomplished by a method and program product that optimizes t... | 01/20/2009 |
| 7478297 | Merged MISR and output register without performance impact for circuits under test The output register of an array and the Multiple Input Signature Register (MISR) logic is implemented with one set of L1/L2 master/slave latches and single additional slave latch. This new combined logic uses less critical area on a chip without a performance impact... | 01/13/2009 |
| 7475193 | Separate data and coherency cache directories in a shared cache in a multiprocessor system A dual system shared cache directory structure for a cache memory performs the role of an inclusive shared system cache, i.e., data, and system control, i.e., coherency. The system includes two separate system cache directories in the shared system cache. The two se... | 01/06/2009 |
| 7469321 | Software process migration between coherency regions without cache purges A multiprocessor computer system has nodes which use processor state information to determine which coherent caches are required to examine a coherency transaction produced by a single originating processor's storage request. A node has dynamic coherency boundaries ... | 12/23/2008 |
| 7469399 | Semi-flattened pin optimization process for hierarchical physical designs In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, ... | 12/23/2008 |
| 7465952 | Programmable non-volatile resistance switching device A memory element comprises a first number of electrodes and a second number of electrically conducting channels between sub-groups of two of said electrodes, the channels exhibiting an electrical resistance that is reversibly switchable between different states, whe... | 12/16/2008 |
| 7463537 | Global bit select circuit interface with dual read and write bit line pairs A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a “local bit select” circuit. ... | 12/09/2008 |
