Did You Know...
...that in the early 1940s GE engineer James Wright was charged with a task of utmost importance to the war effort: develop a cheap substitute for rubber that could be used to produce tires, gas masks and a whole host of military gear. Wright tackled the task diligently -- and wound up inventing Silly Putty.
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| Number | Title | Issue Date |
| 7913136 | Method for performing a logic built-in-self-test in an electronic circuit The present invention relates to a method for performing a logic built-in self-test (LBIST) on an electronic circuit with a plurality of logic circuits (18, 20, 22, 24) and storage elements (14, 16) connected serially to a number of LBIST stumps (10... | 03/22/2011 |
| 7739633 | Verification of highly optimized synchronous pipelines via random simulation driven by critical resource scheduling system and program product Testing a model of a logic circuit model. The testing includes generating valid random input stimulus sequences for a logic circuit model. Enumerating critical resource requirements, enumerating critical resource availabilities does this, and selecting of stimulus s... | 06/15/2010 |
| 7539810 | System, method and storage medium for a multi-mode memory buffer device A multi-mode memory buffer device for use in various memory subsystem structures. The buffer device includes a packetized multi-transfer interface which is redriven to permit connection between a first memory assembly and cascaded memory assemblies. The buffer devic... | 05/26/2009 |
| 7539800 | System, method and storage medium for providing segment level sparing A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multipl... | 05/26/2009 |
| 7529112 | 276-Pin buffered memory module with enhanced fault tolerance and a performance-optimized pin assignment A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a... | 05/05/2009 |
| 7519649 | System and method for performing decimal division A method for performing decimal division including receiving a scaled divisor and dividend and storing a subset of the multiples of the scaled divisor. An accumulated quotient is initialized to be equal to zero, a first current remainder is initialized to be equal t... | 04/14/2009 |
| 7519647 | System and method for providing a decimal multiply algorithm using a double adder A system for performing decimal multiplication including input registers for inputting a multiplier and a multiplicand. The multiplier includes one or more digits. The system also includes one or more two cycle adders and mechanism. The mechanism receives the multip... | 04/14/2009 |
| 7519525 | Post initial microcode load co-simulation method, system, and program product Disclosed is simulation of circuit behavior by running a central electronic core simulation in a high level simulator up to and including initial microload, creation of a post-IML (initial microcode load) state, and transferring the post-initial microcode state from... | 04/14/2009 |
| 7512762 | System, method and storage medium for a memory subsystem with positional read data latency A memory subsystem with positional read data latency that includes a cascaded interconnect system with one or more memory modules, a memory controller and one or more memory busses. The memory controller includes instructions for providing positional read data laten... | 03/31/2009 |
| 7502986 | Method and apparatus for collecting failure information on error correction code (ECC) protected data A method of error correction code (ECC) debugging for a system comprising, receiving data having an ECC, determining whether a data error has occurred, generating a syndrome of an error result, decoding flipped data bits, processing the received data and the decoded... | 03/10/2009 |
| 7502725 | Method, system and computer program product for register management in a simulation environment A method for register management in a simulation environment including receiving an instruction from an instruction unit decode pipeline. An address generation interlock (AGI) function is executed in the simulation environment if the instruction is an AGI instructio... | 03/10/2009 |
| 7493439 | Systems and methods for providing performance monitoring in a memory system Systems and methods for providing performance monitoring in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and ... | 02/17/2009 |
| 7490121 | Modular binary multiplier for signed and unsigned operands of variable widths A method of implementing binary multiplication in a processing device includes obtaining a multiplicand and a multiplier from a storage device; in the event the multiplier is larger than a selected length, partitioning the multiplier into a plurality of multiplier s... | 02/10/2009 |
| 7487484 | Method, system and storage medium for determining circuit placement A method for determining placement of circuitry during integrated circuit design. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list, the individu... | 02/03/2009 |
| 7484161 | System, method and storage medium for providing fault detection and correction in a memory subsystem A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the... | 01/27/2009 |
| 7480759 | System, method and storage medium for providing data caching and data compression in a memory subsystem A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller a... | 01/20/2009 |
| 7480833 | Method and system for performing a hardware trace Methods and systems for pre-detecting a hardware hang in a processor. The methods comprise maintaining a count of a number of cycles in a predefined time interval without an instruction being completed; detecting a pre-hang condition if said count is within N counts... | 01/20/2009 |
| 7480830 | System, method and storage medium for testing a memory module A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnec... | 01/20/2009 |
| 7478259 | System, method and storage medium for deriving clocks in a memory system A system, method and storage medium for deriving clocks in a memory system. The method includes receiving a reference oscillator clock at a hub device. The hub device is in communication with a controller channel via a controller interface and in communication with ... | 01/13/2009 |
| 7477522 | High density high reliability memory module with a fault tolerant address and command bus A high density high reliability memory module with a fault tolerant address and command bus. The memory module includes a rectangular printed circuit board having a first side and a second side, a length of between 149 and 153 millimeters and first and second ends h... | 01/13/2009 |
| 7475316 | System, method and storage medium for providing a high speed test interface to a memory subsystem A buffer device for testing a memory subsystem. The buffer device includes a parallel bus port adapted for connection to a slow speed bus and a serial bus port adapted for connection to a high speed bus. The high speed bus operates at a faster speed than the slow sp... | 01/06/2009 |
| 7475104 | System and method for providing a double adder for decimal floating point operations A system for performing decimal floating point addition. The system includes input registers for inputting a first and second operand for an addition operation. The system also includes a plurality of adder blocks, each calculating a sum of one or more corresponding... | 01/06/2009 |
| 7471219 | Low latency constrained coding for parallel busses A system and method for providing low latency constrained coding for parallel busses. The method includes receiving a value for a number of transfers and a number of possible constrained patterns between adjacent transfer rows. Data to be encoded is received. The da... | 12/30/2008 |
| 7451273 | System, method and storage medium for providing data caching and data compression in a memory subsystem A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller a... | 11/11/2008 |
| 7441060 | System, method and storage medium for providing a service interface to a memory system A cascaded interconnect system for providing a service interface to a memory system. The cascaded interconnect system includes a master service interface module, a service interface bus, and one or more slave service interface modules. The master service interface m... | 10/21/2008 |
| 7441073 | System for indicating a plug position for a memory module in a memory system A memory system including a first and second of set of socket pads adapted for connection to memory module continuity pins. The memory system also includes a first indicator corresponding to the first set of socket pads. The memory system also includes a second indi... | 10/21/2008 |
| 7412476 | Decimal multiplication for superscaler processors A method for decimal multiplication in a superscaler processor comprising: obtaining a first operand and a second operand; establishing a multiplier and an effective multiplicand from the first operand and the second operand; and generating and accumulating a partia... | 08/12/2008 |
| 7403409 | 276-pin buffered memory module with enhanced fault tolerance A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a... | 07/22/2008 |
| 7396244 | Apparatus for extracting and inserting a DIMM An apparatus for extracting and inserting a circuit card into a socket, the apparatus includes a tool device releasably mountable to opposing sides defining the circuit card. The tool device includes a pair of frame members having a friction fit feature for attachme... | 07/08/2008 |
| 7395476 | System, method and storage medium for providing a high speed test interface to a memory subsystem A buffer device for testing a memory subsystem. The buffer device includes a parallel bus port adapted for connection to a slow speed bus and a serial bus port adapted for connection to a high speed bus. The high speed bus operates at a faster speed than the slow sp... | 07/01/2008 |
| 7392337 | System, method and storage medium for a memory subsystem command interface A system for implementing a memory subsystem command interface, the system including a cascaded interconnect system including one or more memory modules, a memory controller and a memory bus. The memory controller generates a data frame that includes a plurality of ... | 06/24/2008 |
| 7389375 | System, method and storage medium for a multi-mode memory buffer device A multi-mode memory buffer device for use in various memory subsystem structures. The buffer device includes a packetized multi-transfer interface which is redriven to permit connection between a first memory assembly and cascaded memory assemblies. The buffer devic... | 06/17/2008 |
| 7380191 | ABIST data compression and serialization for memory built-in self test of SRAM with redundancy A method and apparatus for implementing ABIST data compression and serialization for memory built-in self test of SRAM with redundancy. The method includes providing detection signals asserted for one failing data out, two failing data outs, and greater than two fai... | 05/27/2008 |
| 7380077 | System, method and storage medium for controlling asynchronous updates to a register A system for controlling asynchronous updates to a register, the system including a generally accessible register that is asynchronously updateable by hardware and software. The system also includes protection logic that is in communication with the register. The pr... | 05/27/2008 |
| 7368958 | Methods and systems for locally generating non-integral divided clocks with centralized state machines A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, t... | 05/06/2008 |
| 7356737 | System, method and storage medium for testing a memory module A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnec... | 04/08/2008 |
| 7355460 | Method for locally generating non-integral divided clocks with centralized state machines A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine is provided that includes a counter going through a complete cycle in response to a non-integer number of globa... | 04/08/2008 |
| 7331010 | System, method and storage medium for providing fault detection and correction in a memory subsystem A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the... | 02/12/2008 |
| 7319348 | Circuits for locally generating non-integral divided clocks with centralized state machines Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of glob... | 01/15/2008 |
| 7308527 | System for indicating a plug position for a memory module in a memory system A memory system including a first and second of set of socket pads adapted for connection to memory module continuity pins. The memory system also includes a first indicator corresponding to the first set of socket pads. The memory system also includes a second indi... | 12/11/2007 |
