Did You Know...
...that the Band-Aid Bandage was invented by a Johnson & Johnson employee whose wife had cut herself? Earl Dickson's wife was rather accident prone, so he set out to develop a bandage that she could apply without help. He placed a small piece of gauze in the center of a small piece of surgical tape, and what we know today as the Band Aid bandage was born!
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| Number | Title | Issue Date |
| 5877976 | Memory system having a vertical bitline topology and method therefor An improved topology for multi-port memory cell layouts in which two or more bitline pairs are required for data transfers is provided. Bitlines are displaced vertically, rather than horizontally. Such vertical spacing provides improved silicon density wh... | 03/02/1999 |
| 5877763 | Data processing system and method for viewing objects on a user interface A data processing system and method of operation thereof detect when a situation occurs in which a window displayed on a display device should be brought to a user's attention. That window is then surfaced at the top of a window system z-order of the data... | 03/02/1999 |
| 5875326 | Data processing system and method for completing out-of-order instructions During operation of a pipelined data processing system, an interruptible instruction table is used to store target identifiers associated with instructions which may result in speculative execution. During operation of the interruptible instruction table,... | 02/23/1999 |
| 5623664 | Interactive memory organization system and method therefor A method, referred to as the interactive memory mapper or IMM (322), allows a user to program a memory (9) of a data processor (14) using a computer terminal (12) as a visual interface. The IMM allows a user to view and modify a pictorial representation o... | 04/22/1997 |
| 5619687 | Queue system having a time-out feature and method therefor A queue memory system (10) provides a flexible memory transfer system which uses a single transaction to either store a memory value in a queue or to retrieve the memory value from the queue. A queue controller (20) controls the transfer of data between a... | 04/08/1997 |
| 5608655 | Pager for wireless control and method therefor A wireless paging device (10) is able to control an electronic device (50) at a remote location. The wireless paging device includes a receiver (12) such as those typically used in pagers to detect when a particular electronic device is being remotely acc... | 03/04/1997 |
| 5600811 | Vector move instruction in a vector data processing system and method therefor A "vnmvh" instruction reduces a substantial number of instructions and the temporary use of a register in a software code which executes nested conditional constructs in a vector data processor (10). When the vnmvh instruction is executed, all processing ... | 02/04/1997 |
| 5598571 | Data processor for conditionally modifying extension bits in response to data processing instruction execution A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of ex... | 01/28/1997 |
| 5586217 | Min/max computing circuit for fuzzy inference A fuzzy logic system arranges fuzzy inference rules into groups corresponding to their respective output labels. Within the fuzzy inference rules, the graded input labels are ordered in numerical order according to the grades of each input label such that... | 12/17/1996 |
| 5584031 | System and method for executing a low power delay instruction A system and method is provided for executing a low power no operation instruction in a data processor (10) with a minimal amount of power consumption. In the instruction, an opcode has a mnemonic form of "SLEEP" and an operand which specifies a number of... | 12/10/1996 |
| 5574894 | Integrated circuit data processor which provides external sensibility of internal signals during reset An integrated circuit terminal of a data processing system (10) is used to communicate multiplexed signals with an external device. During a reset operation in which a reset signal is asserted, a desired internal clock signal is driven to the integrated c... | 11/12/1996 |
| 5572689 | Data processing system and method thereof A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of ex... | 11/05/1996 |
| 5561738 | Data processor for executing a fuzzy logic operation and method therefor A fuzzy inference engine (10) performs fuzzy logic operations with a high degree of accuracy in a minimal amount of time. The fuzzy inference engine (10) includes a fuzzification module (12) which decodes an input signal to access a memory location (18, 2... | 10/01/1996 |
| 5559981 | Pseudo static mask option register and method therefor A pseudo-static mask option register (50) combines features of both a continuous refresh design and a static latched mask option register design. Pseudo-static mask option register (50) removes a mask option function from a main user memory (48) such that... | 09/24/1996 |
| 5548768 | Data processing system and method thereof A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of ex... | 08/20/1996 |
| 5535376 | Data processor having a timer circuit for performing a buffered pulse width modulation function and method therefor A timer (28) uses two output-compare timer channels to form a buffered pulse width modulator. A first register (62) and a second register are provided to store a first pulse width value and a second register (66), respectively. When the first register (62... | 07/09/1996 |
| 5502406 | Low power level shift circuit and method therefor A low power level shift and buffer circuit (40) is used to level shift and amplify an output of an oscillator (14, 16, 18, 20, 22, 24) in a data processing application (10). A current mirror (58) and a reference current are used to provide a constant curr... | 03/26/1996 |
| 5485466 | Method and apparatus for performing dual scan path testing of an array in a data processing system A data processing system (10) implements state machine (82) and register logic (80) such that no external control or data is required during execution of a dual scan path test operation. Prior to execution of the dual scan path test operation, a user of d... | 01/16/1996 |
| 5479445 | Mode dependent serial transmission of digital audio information A transceiver (20) communicates audio and non-audio data between a variety of digital audio sources and sinks. Transceiver (20) has a receiver (34, 38) which communicates data between a modulated digital audio source (12) and an unmodulated digital audio ... | 12/26/1995 |
| 5475822 | Data processing system for resuming instruction execution after an interrupt and method therefor The data processing system(10) implements a resumable instruction using two instruction bytes. When a program counter (72) points to a first instruction byte, a first data processing operation is initiated. If an interrupt occurs during execution of the f... | 12/12/1995 |
| 5410721 | System and method for incrementing a program counter A data processor (10) increments a sixteen bit program counter value using an arithmetic logic unit, ALU, (224) and an eight bit incrementer(250). The ALU increments a low byte of the program counter value. A carry generated by incrementing the low byte i... | 04/25/1995 |
| 5410660 | System and method for executing branch on bit set/clear instructions using microprogramming flow A data processing system (10) executes a branch instruction in a straight line microcode sequence. During execution of the instruction, a control unit (56) is provided to decode the instruction to provide a plurality of control signals and to determine a ... | 04/25/1995 |
| 5410270 | Differential amplifier circuit having offset cancellation and method therefor The present invention provides a circuit (10) and method for sampling a single-ended signal and then converting the single-ended signal to a differential signal. After the single-ended signal is converted to a differential signal, then the offset voltage ... | 04/25/1995 |
| 5404386 | Programmable clock for an analog converter in a data processor and method therefor A data processing system (10) includes a programmable clock signal for an analog converter (28). A duty cycle of the programmable clock signal is programmed by an external user in a prescaler rate selection register (16). A counter subsequently counts for... | 04/04/1995 |
| 5398299 | Min-max computing circuit for fuzzy inference In a fuzzy inference system comprising a plurality of fuzzy rules including input labels as antecedents, a min-max computing circuit for executing min-max computation on input label grades is disclosed. The min-max computing circuit comprises an input lab... | 03/14/1995 |
| 5394444 | Lock detect circuit for detecting a lock condition in a phase locked loop and method therefor A lock detect circuit (18) determines when a reference frequency and a feedback frequency are frequency locked using a reference counter (32) and a feedback counter (36). The reference counter (32) and the feedback counter (36) are clocked by the referenc... | 02/28/1995 |
| 5392348 | DTMF detection having sample rate decimation and adaptive tone detection A method of dual-tone multifrequency (DTMF) detection which decimates and adaptively filters an input signal is provided to efficiently detect a presence of a DTMF signal. The input signal is provided to a half-band filter (14) to be decimated in frequenc... | 02/21/1995 |
| 5386534 | Data processing system for generating symmetrical range of addresses of instructing-address-value with the use of inverting sign value A data processing system (10) performs indexed addressing, autoincrementing, and autodecrementing using power of two byte boundaries. For example, a 5-bit offset allows a user to progress sixteen bytes either forward or backward through a table of data. A... | 01/31/1995 |
| 5383137 | Emulation system and method for development of a low power data processor An emulation system (10) provides a plurality of circuits (20,28) which each emulate operation of a predetermined component of a target microprocessor (24). Each of the plurality of circuits (20,28) imitates a corresponding component of the target micropr... | 01/17/1995 |
| 5375216 | Apparatus and method for optimizing performance of a cache memory in a data processing system A circuit for allowing greater user control over a cache memory is implemented in a data processor (20). Cache control instructions have been implemented to perform touch load, flush, and allocate operations in data cache (54) of data cache unit (24). The... | 12/20/1994 |
| 5367494 | Randomly accessible memory having time overlapping memory accesses A memory device (28) executes memory access operations of two or more storage locations concurrently. The memory device (28) is comprised of a plurality of memory bank decode logic circuits (30, 32, 56) and a plurality of memory banks (34, 52). Each of th... | 11/22/1994 |
| 5359626 | Serial interface bus system for transmitting and receiving digital audio information A serial interface bus system for transmitting and receiving a plurality of bus signals which collectively allow communication of data between a digital audio source (12, 22, 24, 26, 56, 82) such as a compact disc and a digital sink (42, 52, 62, 64, 66) s... | 10/25/1994 |
| 5341500 | Data processor with combined static and dynamic masking of operand for breakpoint operation A data processing system (10) implements a combined static and a dynamic masking operation of a breakpoint address. A static mask implements a conditional mask of a predetermined number of bits specified by the user and is determined prior to a comparison... | 08/23/1994 |
| 5319763 | Data processor with concurrent static and dynamic masking of operand information and method therefor A data processing system (10) implements a static and a dynamic masking operation of operand information concurrently. A static mask implements a conditional mask of a predetermined number of bits specified by the user and is determined prior to a compari... | 06/07/1994 |
| 5304855 | Bi-level pulse accumulator A pulse accumulator (24) operates in a pulse measurement mode. In the pulse measurement mode, accumulator (24) measured pulse lengths of consecutive high and low input signal pulses in reference to a clock signal. A leading-edge capture circuit (50) asser... | 04/19/1994 |
| 5301345 | Data processing system for performing a shifting operation and a constant generation operation and method therefor A data processing system (10) has a control selector (30) which has at least one conductor used for the common functions of shifting data and controling the generation of constants in an execution unit (26). A logic circuit (34) provides control signals t... | 04/05/1994 |
| 5295229 | Circuit and method for determining membership in a set during a fuzzy logic operation A circuit (14) and method which determine a degree of membership of an input in a membership set during a fuzzy logic operation. The degree of membership is calculated by a single "MEM" software instruction. The MEM instruction determines whether the syst... | 03/15/1994 |
| 5278874 | Phase lock loop frequency correction circuit A phase lock loop circuit (10) which locks to a frequency within a range of input signal frequencies. A frequency discriminator (12) of phase lock loop circuit (10) determines a maximum pulse width of the input signal by counting a number of pulses of a r... | 01/11/1994 |
| 5263168 | Circuitry for automatically entering and terminating an initialization mode in a data processing system in response to a control signal A data processing system (10), comprised of a central processing unit (14) and a memory system (16), has an efficient initialization operation. The memory system (16) provides a bus interface unit (20) to automatically determine whether the system (10) sh... | 11/16/1993 |
| 5263125 | Circuit and method for evaluating fuzzy logic rules A circuit (14) to evaluate a plurality of fuzzy logic rules in a data processor (10) in response to a single "REV" software instruction. The REV instruction evaluates the rules stored in a memory (32) to determine a rule strength of each. Antecedents are ... | 11/16/1993 |
